From: Khalil Blaiech <kblaiech@nvidia.com>
Date: Tue, 3 Nov 2020 14:54:41 -0500
Subject: i2c: mlxbf: Update reference clock frequency
Git-commit: 67ee9fda6ed4958f4caf8f1a3a5102a2c27ddf7b
Patch-mainline: v5.10-rc3
References: jsc#SLE-15271 jsc#SLE-16108 jsc#SLE-16098 jsc#SLE-13565
The reference clock frequency remains the same across Bluefield
products. Thus, update the frequency and rename the macro.
Fixes: b5b5b32081cd206b ("i2c: mlxbf: I2C SMBus driver for Mellanox BlueField SoC")
Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Khalil Blaiech <kblaiech@nvidia.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
drivers/i2c/busses/i2c-mlxbf.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mlxbf.c b/drivers/i2c/busses/i2c-mlxbf.c
index fca8a3bddcb1..afc996d07504 100644
--- a/drivers/i2c/busses/i2c-mlxbf.c
+++ b/drivers/i2c/busses/i2c-mlxbf.c
@@ -62,10 +62,8 @@
* Master. Default value is set to 400MHz.
*/
#define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000)
-/* Reference clock for Bluefield 1 - 156 MHz. */
-#define MLXBF_I2C_TYU_PLL_IN_FREQ (156 * 1000 * 1000)
-/* Reference clock for BlueField 2 - 200 MHz. */
-#define MLXBF_I2C_YU_PLL_IN_FREQ (200 * 1000 * 1000)
+/* Reference clock for Bluefield - 156 MHz. */
+#define MLXBF_I2C_PLL_IN_FREQ (156 * 1000 * 1000)
/* Constant used to determine the PLL frequency. */
#define MLNXBF_I2C_COREPLL_CONST 16384
@@ -1422,7 +1420,7 @@ static u64 mlxbf_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res)
u32 corepll_val;
u16 core_f;
- pad_frequency = MLXBF_I2C_TYU_PLL_IN_FREQ;
+ pad_frequency = MLXBF_I2C_PLL_IN_FREQ;
corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
@@ -1457,7 +1455,7 @@ static u64 mlxbf_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res)
u8 core_od, core_r;
u32 core_f;
- pad_frequency = MLXBF_I2C_YU_PLL_IN_FREQ;
+ pad_frequency = MLXBF_I2C_PLL_IN_FREQ;
corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2);
--
2.30.0