From: Marc Zyngier <maz@kernel.org>
Date: Sun, 9 Feb 2020 22:48:50 +0000
Subject: irqchip/gic-v4.1: Avoid 64bit division for the sake of 32bit ARM
Git-commit: 490d332ea42780577f679f5d13598b195bff360c
Patch-mainline: v5.6-rc1
References: jsc#SLE-14773 jsc#SLE-14763
In order to allow the GICv4 code to link properly on 32bit ARM,
make sure we don't use 64bit divisions when it isn't strictly
necessary.
Fixes: 4e6437f12d6e ("irqchip/gic-v4.1: Ensure L2 vPE table is allocated at RD level")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
drivers/irqchip/irq-gic-v3-its.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 1ee95f546cb0..83b1186ffcad 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2444,8 +2444,8 @@ static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask)
static bool allocate_vpe_l2_table(int cpu, u32 id)
{
void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
- u64 val, gpsz, npg;
- unsigned int psz, esz, idx;
+ unsigned int psz, esz, idx, npg, gpsz;
+ u64 val;
struct page *page;
__le64 *table;
--
2.28.0