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Subject: drm/amdgpu: always flush the TLB on gfx8
From: "=?UTF-8?q?Christian=20K=C3=B6nig?=" <ckoenig.leichtzumerken@gmail.com>
X-Patchwork-Id: 488258
Message-Id: <20220603130504.81147-1-christian.koenig@amd.com>
Date: Fri,  3 Jun 2022 15:05:04 +0200
Patch-mainline: submitted - 2022-06-03 - 20220603130504.81147-1-christian.koenig@amd.com
References: https://lists.freedesktop.org/archives/amd-gfx/2022-May/079700.html

The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits
are set.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Michal Kubecek <mkubecek@suse.cz>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++
 1 file changed, 5 insertions(+)

--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -847,6 +847,11 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
 		     adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
 
+	/*
+	 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
+	 */
+	flush_tlb |= adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 0);
+
 	memset(&params, 0, sizeof(params));
 	params.adev = adev;
 	params.vm = vm;