From 3d02352cd9e8b43805bf68e50e395fda2e218791 Mon Sep 17 00:00:00 2001
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Date: Fri, 2 Jun 2017 13:06:43 -0700
Subject: [PATCH] drm/i915/cnp: add CNP gmbus support
Git-commit: 3d02352cd9e8b43805bf68e50e395fda2e218791
Patch-mainline: 4.13-rc1
References: FATE#322643 bsc#1055900
On CNP PCH based platforms the gmbus is on the south display that
is on PCH. The existing implementation for previous platforms
already covers the need for CNP expect for the pin pair configuration
that follows similar definitions that we had on BXT.
V2: Don't drop "_BXT" as the indicator of the first platform supporting this pin numbers. Suggested by Daniel.
V3: Add missing else and fix register table since CNP GPIO_CTL starts on 0xC5014.
V4: Fix pin number and map according to the current available VBT. Re-add pin 4 for port D. Lost during some rebase.
V5: Use table as spec. If VBT is wrong it should be ignored.
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1496434004-29812-5-git-send-email-rodrigo.vivi@intel.com
Acked-by: Takashi Iwai <tiwai@suse.de>
---
drivers/gpu/drm/i915/i915_reg.h | 3 ++-
drivers/gpu/drm/i915/intel_hdmi.c | 8 +++++---
drivers/gpu/drm/i915/intel_i2c.c | 15 +++++++++++++--
3 files changed, 20 insertions(+), 6 deletions(-)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2618,9 +2618,10 @@ enum skl_disp_power_wells {
#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
#define GMBUS_PIN_DPD 6 /* HDMID */
#define GMBUS_PIN_RESERVED 7 /* 7 reserved */
-#define GMBUS_PIN_1_BXT 1
+#define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
#define GMBUS_PIN_2_BXT 2
#define GMBUS_PIN_3_BXT 3
+#define GMBUS_PIN_4_CNP 4
#define GMBUS_NUM_PINS 7 /* including 0 */
#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
#define GMBUS_SW_CLR_INT (1<<31)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1892,19 +1892,21 @@ static u8 intel_hdmi_ddc_pin(struct drm_
switch (port) {
case PORT_B:
- if (IS_GEN9_LP(dev_priv))
+ if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
ddc_pin = GMBUS_PIN_1_BXT;
else
ddc_pin = GMBUS_PIN_DPB;
break;
case PORT_C:
- if (IS_GEN9_LP(dev_priv))
+ if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
ddc_pin = GMBUS_PIN_2_BXT;
else
ddc_pin = GMBUS_PIN_DPC;
break;
case PORT_D:
- if (IS_CHERRYVIEW(dev_priv))
+ if (HAS_PCH_CNP(dev_priv))
+ ddc_pin = GMBUS_PIN_4_CNP;
+ else if (IS_CHERRYVIEW(dev_priv))
ddc_pin = GMBUS_PIN_DPD_CHV;
else
ddc_pin = GMBUS_PIN_DPD;
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -68,11 +68,20 @@ static const struct gmbus_pin gmbus_pins
[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
};
+static const struct gmbus_pin gmbus_pins_cnp[] = {
+ [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
+ [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
+ [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+};
+
/* pin is expected to be valid */
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (IS_GEN9_LP(dev_priv))
+ if (HAS_PCH_CNP(dev_priv))
+ return &gmbus_pins_cnp[pin];
+ else if (IS_GEN9_LP(dev_priv))
return &gmbus_pins_bxt[pin];
else if (IS_GEN9_BC(dev_priv))
return &gmbus_pins_skl[pin];
@@ -87,7 +96,9 @@ bool intel_gmbus_is_valid_pin(struct drm
{
unsigned int size;
- if (IS_GEN9_LP(dev_priv))
+ if (HAS_PCH_CNP(dev_priv))
+ size = ARRAY_SIZE(gmbus_pins_cnp);
+ else if (IS_GEN9_LP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_bxt);
else if (IS_GEN9_BC(dev_priv))
size = ARRAY_SIZE(gmbus_pins_skl);