From bd5446149c6ac9d473695fc8e77fb4e410ae07be Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 15 Jul 2021 12:35:20 +0300
Subject: drm/i915: Extract ilk_update_pll_dividers()
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Git-commit: b294425e9091239330dcb9d3aa3ac160ca05d0e7
Patch-mainline: v5.16-rc1
References: jsc#PED-1166 jsc#PED-1168 jsc#PED-1170 jsc#PED-1218 jsc#PED-1220 jsc#PED-1222 jsc#PED-1223 jsc#PED-1225
Make the PCH dpll code match the gmch code by splitting
the FP register handling out from ilk_compute_dpll().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 25 +++++++++++++++--------
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 939a1a6e5c1e..e2ca6f2108d1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -948,12 +948,12 @@ static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
}
-static void ilk_compute_dpll(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct dpll *reduced_clock)
+static void ilk_update_pll_dividers(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state,
+ struct dpll *reduced_clock)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 dpll, fp, fp2;
+ u32 fp, fp2 = 0;
int factor;
/* Enable autotuning of the PLL clock (if permissible) */
@@ -978,10 +978,21 @@ static void ilk_compute_dpll(struct intel_crtc *crtc,
if (reduced_clock->m < factor * reduced_clock->n)
fp2 |= FP_CB_TUNE;
- } else {
- fp2 = fp;
}
+ crtc_state->dpll_hw_state.fp0 = fp;
+ crtc_state->dpll_hw_state.fp1 = reduced_clock ? fp2 : fp;
+}
+
+static void ilk_compute_dpll(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state,
+ struct dpll *reduced_clock)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 dpll;
+
+ ilk_update_pll_dividers(crtc, crtc_state, reduced_clock);
+
dpll = 0;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
@@ -1046,8 +1057,6 @@ static void ilk_compute_dpll(struct intel_crtc *crtc,
dpll |= DPLL_VCO_ENABLE;
crtc_state->dpll_hw_state.dpll = dpll;
- crtc_state->dpll_hw_state.fp0 = fp;
- crtc_state->dpll_hw_state.fp1 = fp2;
}
static int ilk_crtc_compute_clock(struct intel_crtc *crtc,
--
2.38.1