From 3bf2dd9303d894eadecd4dc0cdf7670369061167 Mon Sep 17 00:00:00 2001
From: Huang Rui <ray.huang@amd.com>
Date: Fri, 20 May 2022 11:04:04 +0800
Subject: drm/amdgpu: introduce two work mode for imu
Git-commit: 542a0f2ef9ea2ccfadf2b8a3b53368c61fc97a0f
Patch-mainline: v6.0-rc1
References: jsc#PED-1166 jsc#PED-1168 jsc#PED-1170 jsc#PED-1218 jsc#PED-1220 jsc#PED-1222 jsc#PED-1223 jsc#PED-1225 jsc#PED-2849
IMU has two work mode such as debug mode and mission mode. Current GC
v11_0_0 is using the debug mode.
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h | 6 +++++
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 30 ++++++++++++++-----------
3 files changed, 24 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
index 56cf127cdf93..cfc4a92837f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
@@ -24,6 +24,11 @@
#ifndef __AMDGPU_IMU_H__
#define __AMDGPU_IMU_H__
+enum imu_work_mode {
+ DEBUG_MODE,
+ MISSION_MODE
+};
+
struct amdgpu_imu_funcs {
int (*init_microcode)(struct amdgpu_device *adev);
int (*load_microcode)(struct amdgpu_device *adev);
@@ -46,6 +51,7 @@ struct imu_rlc_ram_golden {
struct amdgpu_imu {
const struct amdgpu_imu_funcs *funcs;
+ enum imu_work_mode mode;
};
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index a4a6751b1e44..da4590b25b0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -6293,6 +6293,7 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev)
{
+ adev->gfx.imu.mode = DEBUG_MODE;
adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
index d63d3f2b8a16..05d2b93a534c 100644
--- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
@@ -125,9 +125,11 @@ static void imu_v11_0_setup(struct amdgpu_device *adev)
WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff);
WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff);
- imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);
- imu_reg_val |= 0x1;
- WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);
+ if (adev->gfx.imu.mode == DEBUG_MODE) {
+ imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);
+ imu_reg_val |= 0x1;
+ WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);
+ }
//disble imu Rtavfs, SmsRepair, DfllBTC, and ClkB
imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10);
@@ -144,16 +146,18 @@ static int imu_v11_0_start(struct amdgpu_device *adev)
imu_reg_val &= 0xfffffffe;
WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);
- for (i = 0; i < adev->usec_timeout; i++) {
- imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
- if ((imu_reg_val & 0x1f) == 0x1f)
- break;
- udelay(1);
- }
-
- if (i >= adev->usec_timeout) {
- dev_err(adev->dev, "init imu: IMU start timeout\n");
- return -ETIMEDOUT;
+ if (adev->gfx.imu.mode == DEBUG_MODE) {
+ for (i = 0; i < adev->usec_timeout; i++) {
+ imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
+ if ((imu_reg_val & 0x1f) == 0x1f)
+ break;
+ udelay(1);
+ }
+
+ if (i >= adev->usec_timeout) {
+ dev_err(adev->dev, "init imu: IMU start timeout\n");
+ return -ETIMEDOUT;
+ }
}
return 0;
--
2.38.1