From: Shay Drory <shayd@nvidia.com>
Date: Wed, 16 Jun 2021 18:58:26 +0300
Subject: net/mlx5: Align mlx5_irq structure
Patch-mainline: v5.15-rc1
Git-commit: 211f4f99edc0d2cd909f1a37561573f7b7d9fc42
References: jsc#SLE-19253
mlx5_irq structure have holes due to incorrect position of fields in it.
Make them naturally align.
pahole output after alignment:
struct mlx5_irq {
struct atomic_notifier_head nh; /* 0 72 */
/* --- cacheline 1 boundary (64 bytes) was 8 bytes ago --- */
cpumask_var_t mask; /* 72 8 */
char name[32]; /* 80 32 */
struct mlx5_irq_pool * pool; /* 112 8 */
struct kref kref; /* 120 4 */
u32 index; /* 124 4 */
/* --- cacheline 2 boundary (128 bytes) --- */
int irqn; /* 128 4 */
/* size: 136, cachelines: 3, members: 7 */
/* padding: 4 */
/* last cacheline: 8 bytes */
};
Signed-off-by: Shay Drory <shayd@nvidia.com>
Reviewed-by: Parav Pandit <parav@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
---
drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c
@@ -28,13 +28,13 @@
#define MLX5_EQ_REFS_PER_IRQ (2)
struct mlx5_irq {
- u32 index;
struct atomic_notifier_head nh;
cpumask_var_t mask;
char name[MLX5_MAX_IRQ_NAME];
+ struct mlx5_irq_pool *pool;
struct kref kref;
+ u32 index;
int irqn;
- struct mlx5_irq_pool *pool;
};
struct mlx5_irq_pool {