From 7b3b3928eff01dcb9859ee57bead835a3416d1c1 Mon Sep 17 00:00:00 2001
From: Tom St Denis <tom.stdenis@amd.com>
Date: Tue, 9 Jun 2020 07:49:59 -0400
Subject: drm/amd/amdgpu: Add SQ debug registers to GFX9/GFX10 headers (v2)
Git-commit: 055e23e3d9ea1d680977f8e34f9678c17cb3cfc1
Patch-mainline: v5.9-rc1
References: jsc#SLE-12680, jsc#SLE-12880, jsc#SLE-12882, jsc#SLE-12883, jsc#SLE-13496, jsc#SLE-15322
Requested for UMR support.
(v2): Also add reg/bits for gfx9 headers
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Patrik Jakobsson <pjakobsson@suse.de>
---
.../include/asic_reg/gc/gc_10_1_0_offset.h | 1 +
.../include/asic_reg/gc/gc_10_1_0_sh_mask.h | 20 +++++++++++++++++++
.../include/asic_reg/gc/gc_10_3_0_offset.h | 1 +
.../include/asic_reg/gc/gc_10_3_0_sh_mask.h | 19 ++++++++++++++++++
.../amd/include/asic_reg/gc/gc_9_0_offset.h | 1 +
.../amd/include/asic_reg/gc/gc_9_0_sh_mask.h | 5 +++++
.../amd/include/asic_reg/gc/gc_9_1_offset.h | 1 +
.../amd/include/asic_reg/gc/gc_9_1_sh_mask.h | 5 +++++
.../amd/include/asic_reg/gc/gc_9_2_1_offset.h | 1 +
.../include/asic_reg/gc/gc_9_2_1_sh_mask.h | 5 +++++
10 files changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
index 075867d4b1da..791dc2b3d74a 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
@@ -11151,6 +11151,7 @@
// addressBlock: sqind
// base address: 0x0
+#define ixSQ_DEBUG_STS_LOCAL 0x0008
#define ixSQ_WAVE_MODE 0x0101
#define ixSQ_WAVE_STATUS 0x0102
#define ixSQ_WAVE_TRAPSTS 0x0103
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
index 8b0b9a2a8fed..355e61bed291 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
@@ -42546,6 +42546,26 @@
// addressBlock: sqind
+//SQ_DEBUG_STS_LOCAL
+#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L
+#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004
+#define SQ_DEBUG_STS_LOCAL__SQ_BUSY_MASK 0x00001000L
+#define SQ_DEBUG_STS_LOCAL__SQ_BUSY__SHIFT 0x0000000C
+#define SQ_DEBUG_STS_LOCAL__IS_BUSY_MASK 0x00002000L
+#define SQ_DEBUG_STS_LOCAL__IS_BUSY__SHIFT 0x0000000D
+#define SQ_DEBUG_STS_LOCAL__IB_BUSY_MASK 0x00004000L
+#define SQ_DEBUG_STS_LOCAL__IB_BUSY__SHIFT 0x0000000E
+#define SQ_DEBUG_STS_LOCAL__ARB_BUSY_MASK 0x00008000L
+#define SQ_DEBUG_STS_LOCAL__ARB_BUSY__SHIFT 0x0000000F
+#define SQ_DEBUG_STS_LOCAL__EXP_BUSY_MASK 0x00010000L
+#define SQ_DEBUG_STS_LOCAL__EXP_BUSY__SHIFT 0x00000010
+#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY_MASK 0x00020000L
+#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY__SHIFT 0x00000011
+#define SQ_DEBUG_STS_LOCAL__VM_BUSY_MASK 0x00040000L
+#define SQ_DEBUG_STS_LOCAL__VM_BUSY__SHIFT 0x00000018
+
//SQ_WAVE_MODE
#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
index 71c787d66132..a9a66371b75e 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
@@ -13277,6 +13277,7 @@
// addressBlock: sqind
// base address: 0x0
+#define ixSQ_DEBUG_STS_LOCAL 0x0008
#define ixSQ_WAVE_ACTIVE 0x000a
#define ixSQ_WAVE_VALID_AND_IDLE 0x000b
#define ixSQ_WAVE_MODE 0x0101
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
index 00bae8e09f84..499a8c3c2693 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
@@ -46269,6 +46269,25 @@
// addressBlock: sqind
+//SQ_DEBUG_STS_LOCAL
+#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L
+#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004
+#define SQ_DEBUG_STS_LOCAL__SQ_BUSY_MASK 0x00001000L
+#define SQ_DEBUG_STS_LOCAL__SQ_BUSY__SHIFT 0x0000000C
+#define SQ_DEBUG_STS_LOCAL__IS_BUSY_MASK 0x00002000L
+#define SQ_DEBUG_STS_LOCAL__IS_BUSY__SHIFT 0x0000000D
+#define SQ_DEBUG_STS_LOCAL__IB_BUSY_MASK 0x00004000L
+#define SQ_DEBUG_STS_LOCAL__IB_BUSY__SHIFT 0x0000000E
+#define SQ_DEBUG_STS_LOCAL__ARB_BUSY_MASK 0x00008000L
+#define SQ_DEBUG_STS_LOCAL__ARB_BUSY__SHIFT 0x0000000F
+#define SQ_DEBUG_STS_LOCAL__EXP_BUSY_MASK 0x00010000L
+#define SQ_DEBUG_STS_LOCAL__EXP_BUSY__SHIFT 0x00000010
+#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY_MASK 0x00020000L
+#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY__SHIFT 0x00000011
+#define SQ_DEBUG_STS_LOCAL__VM_BUSY_MASK 0x00040000L
+#define SQ_DEBUG_STS_LOCAL__VM_BUSY__SHIFT 0x00000018
//SQ_WAVE_ACTIVE
#define SQ_WAVE_ACTIVE__WAVE_SLOT__SHIFT 0x0
#define SQ_WAVE_ACTIVE__WAVE_SLOT_MASK 0x000FFFFFL
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
index d984c916df80..fc39795acfda 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
@@ -7088,6 +7088,7 @@
// addressBlock: sqind
// base address: 0x0
+#define ixSQ_DEBUG_STS_LOCAL 0x0008
#define ixSQ_WAVE_MODE 0x0011
#define ixSQ_WAVE_STATUS 0x0012
#define ixSQ_WAVE_TRAPSTS 0x0013
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
index ea316d8dcb37..d7964c2bd950 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
@@ -28350,6 +28350,11 @@
// addressBlock: sqind
+//SQ_DEBUG_STS_LOCAL
+#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L
+#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004
//SQ_WAVE_MODE
#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
index 030e0020902b..2223d4b77dcb 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
@@ -7296,6 +7296,7 @@
// addressBlock: sqind
// base address: 0x0
+#define ixSQ_DEBUG_STS_LOCAL 0x0008
#define ixSQ_WAVE_MODE 0x0011
#define ixSQ_WAVE_STATUS 0x0012
#define ixSQ_WAVE_TRAPSTS 0x0013
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
index 13bfc2e6e16f..4acf640b1893 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
@@ -29571,6 +29571,11 @@
// addressBlock: sqind
+//SQ_DEBUG_STS_LOCAL
+#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L
+#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004
//SQ_WAVE_MODE
#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
index 5ab240cc9891..1c5ef8e8a341 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
@@ -7335,6 +7335,7 @@
// addressBlock: sqind
// base address: 0x0
+#define ixSQ_DEBUG_STS_LOCAL 0x0008
#define ixSQ_WAVE_MODE 0x0011
#define ixSQ_WAVE_STATUS 0x0012
#define ixSQ_WAVE_TRAPSTS 0x0013
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h
index 76ea902340c1..088f59cc2197 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h
@@ -29893,6 +29893,11 @@
// addressBlock: sqind
+//SQ_DEBUG_STS_LOCAL
+#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L
+#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004
//SQ_WAVE_MODE
#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
--
2.29.2