From f81b86a043270eb5f7e3a80354bea88d0b43ff6f Mon Sep 17 00:00:00 2001
From: Oak Zeng <Oak.Zeng@amd.com>
Date: Mon, 7 Oct 2019 15:32:23 -0500
Subject: drm/amdgpu: Enable gfx cache probing on HDP write for arcturus
Git-commit: f81b86a043270eb5f7e3a80354bea88d0b43ff6f
Patch-mainline: v5.5-rc1
References: bsc#1152489
This allows gfx cache to be probed and invalidated (for none-dirty cache lines)
on a HDP write (from either another GPU or CPU). This should work only for the
memory mapped as RW memory type newly added for arcturus, to achieve some cache
coherence b/t multiple memory clients.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Christian Konig <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 12bbccdd9d1c..9f2a893871ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1194,6 +1194,9 @@ static int gmc_v9_0_hw_init(void *handle)
/* TODO for renoir */
mmhub_v1_0_update_power_gating(adev, true);
break;
+ case CHIP_ARCTURUS:
+ WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
+ break;
default:
break;
}
--
2.28.0