From c77a35c4c0480ea68afebb756b4637804c401b4e Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 15 Jan 2020 06:34:21 +1000
Subject: drm/nouveau/sec2: initialise SW state for falcon from constructor
Git-commit: edd757d17891b5330a5dbc1ce0bb710a5017e530
Patch-mainline: v5.6-rc1
References: jsc#SLE-12680, jsc#SLE-12880, jsc#SLE-12882, jsc#SLE-12883, jsc#SLE-13496, jsc#SLE-15322
This will allow us to register the falcon with ACR, and further customise
its behaviour by providing the nvkm_falcon_func structure directly.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Patrik Jakobsson <pjakobsson@suse.de>
---
.../drm/nouveau/include/nvkm/engine/sec2.h | 3 ++-
.../gpu/drm/nouveau/nvkm/engine/sec2/base.c | 25 +++++--------------
.../gpu/drm/nouveau/nvkm/engine/sec2/gp102.c | 18 ++++++++++++-
.../gpu/drm/nouveau/nvkm/engine/sec2/priv.h | 1 +
.../gpu/drm/nouveau/nvkm/engine/sec2/tu102.c | 15 +++++++++++
.../nouveau/nvkm/subdev/secboot/acr_r361.c | 2 +-
.../nouveau/nvkm/subdev/secboot/acr_r370.c | 2 +-
.../drm/nouveau/nvkm/subdev/secboot/base.c | 2 +-
.../nvkm/subdev/secboot/ls_ucode_msgqueue.c | 4 +--
9 files changed, 46 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h
index b9ef4472c20e..2ffa125a15d7 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h
@@ -3,13 +3,14 @@
#define __NVKM_SEC2_H__
#define nvkm_sec2(p) container_of((p), struct nvkm_sec2, engine)
#include <core/engine.h>
+#include <core/falcon.h>
struct nvkm_sec2 {
const struct nvkm_sec2_func *func;
struct nvkm_engine engine;
+ struct nvkm_falcon falcon;
u32 addr;
- struct nvkm_falcon *falcon;
struct nvkm_msgqueue *queue;
struct work_struct work;
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c
index 50c183347cae..5554e9f4df88 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c
@@ -24,7 +24,6 @@
#include <core/firmware.h>
#include <core/msgqueue.h>
#include <subdev/top.h>
-#include <engine/falcon.h>
static void
nvkm_sec2_intr(struct nvkm_engine *engine)
@@ -62,22 +61,6 @@ nvkm_sec2_recv(struct work_struct *work)
nvkm_msgqueue_recv(sec2->queue);
}
-
-static int
-nvkm_sec2_oneinit(struct nvkm_engine *engine)
-{
- struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
- struct nvkm_subdev *subdev = &sec2->engine.subdev;
-
- if (!sec2->addr) {
- sec2->addr = nvkm_top_addr(subdev->device, subdev->index);
- if (WARN_ON(!sec2->addr))
- return -EINVAL;
- }
-
- return nvkm_falcon_v1_new(subdev, "SEC2", sec2->addr, &sec2->falcon);
-}
-
static int
nvkm_sec2_fini(struct nvkm_engine *engine, bool suspend)
{
@@ -91,14 +74,13 @@ nvkm_sec2_dtor(struct nvkm_engine *engine)
{
struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
nvkm_msgqueue_del(&sec2->queue);
- nvkm_falcon_del(&sec2->falcon);
+ nvkm_falcon_dtor(&sec2->falcon);
return sec2;
}
static const struct nvkm_engine_func
nvkm_sec2 = {
.dtor = nvkm_sec2_dtor,
- .oneinit = nvkm_sec2_oneinit,
.fini = nvkm_sec2_fini,
.intr = nvkm_sec2_intr,
};
@@ -124,6 +106,11 @@ nvkm_sec2_new_(const struct nvkm_sec2_fwif *fwif, struct nvkm_device *device,
sec2->func = fwif->func;
+ ret = nvkm_falcon_ctor(sec2->func->flcn, &sec2->engine.subdev,
+ nvkm_subdev_name[index], addr, &sec2->falcon);
+ if (ret)
+ return ret;
+
INIT_WORK(&sec2->work, nvkm_sec2_recv);
return 0;
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
index befeee374cc6..75407cb8a88a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
@@ -26,8 +26,24 @@ static const struct nvkm_acr_lsf_func
gp102_sec2_acr_0 = {
};
+
+static const struct nvkm_falcon_func
+gp102_sec2_flcn = {
+ .load_imem = nvkm_falcon_v1_load_imem,
+ .load_dmem = nvkm_falcon_v1_load_dmem,
+ .read_dmem = nvkm_falcon_v1_read_dmem,
+ .bind_context = nvkm_falcon_v1_bind_context,
+ .wait_for_halt = nvkm_falcon_v1_wait_for_halt,
+ .clear_interrupt = nvkm_falcon_v1_clear_interrupt,
+ .set_start_addr = nvkm_falcon_v1_set_start_addr,
+ .start = nvkm_falcon_v1_start,
+ .enable = nvkm_falcon_v1_enable,
+ .disable = nvkm_falcon_v1_disable,
+};
+
const struct nvkm_sec2_func
gp102_sec2 = {
+ .flcn = &gp102_sec2_flcn,
};
MODULE_FIRMWARE("nvidia/gp102/sec2/desc.bin");
@@ -52,7 +68,7 @@ gp102_sec2_load(struct nvkm_sec2 *sec2, int ver,
const struct nvkm_sec2_fwif *fwif)
{
return nvkm_acr_lsfw_load_sig_image_desc_v1(&sec2->engine.subdev,
- sec2->falcon,
+ &sec2->falcon,
NVKM_ACR_LSF_SEC2, "sec2/",
ver, fwif->acr);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h
index d37d315295b5..6e28b969573b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h
@@ -4,6 +4,7 @@
#include <engine/sec2.h>
struct nvkm_sec2_func {
+ const struct nvkm_falcon_func *flcn;
};
struct nvkm_sec2_fwif {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c
index c8258658b503..5192b3a1e40c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c
@@ -21,8 +21,23 @@
*/
#include "priv.h"
+static const struct nvkm_falcon_func
+tu102_sec2_flcn = {
+ .load_imem = nvkm_falcon_v1_load_imem,
+ .load_dmem = nvkm_falcon_v1_load_dmem,
+ .read_dmem = nvkm_falcon_v1_read_dmem,
+ .bind_context = nvkm_falcon_v1_bind_context,
+ .wait_for_halt = nvkm_falcon_v1_wait_for_halt,
+ .clear_interrupt = nvkm_falcon_v1_clear_interrupt,
+ .set_start_addr = nvkm_falcon_v1_set_start_addr,
+ .start = nvkm_falcon_v1_start,
+ .enable = nvkm_falcon_v1_enable,
+ .disable = nvkm_falcon_v1_disable,
+};
+
static const struct nvkm_sec2_func
tu102_sec2 = {
+ .flcn = &tu102_sec2_flcn,
};
static int
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c
index 513445856f22..e6dd0a4bf581 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c
@@ -172,7 +172,7 @@ acr_r361_generate_sec2_bl_desc(const struct nvkm_acr *acr,
/* For some reason we should not add app_resident_code_offset here */
addr_code = base;
addr_data = base + pdesc->app_resident_data_offset;
- addr_args = sec->falcon->data.limit;
+ addr_args = sec->falcon.data.limit;
addr_args -= NVKM_MSGQUEUE_CMDLINE_SIZE;
desc->dma_idx = FALCON_SEC2_DMAIDX_UCODE;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c
index e821d0fd6217..f850c3be261a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c
@@ -96,7 +96,7 @@ acr_r370_generate_sec2_bl_desc(const struct nvkm_acr *acr,
/* For some reason we should not add app_resident_code_offset here */
addr_code = base;
addr_data = base + pdesc->app_resident_data_offset;
- addr_args = sec->falcon->data.limit;
+ addr_args = sec->falcon.data.limit;
addr_args -= NVKM_MSGQUEUE_CMDLINE_SIZE;
desc->ctx_dma = FALCON_SEC2_DMAIDX_UCODE;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c
index 36ae6918beae..993f01b1d155 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c
@@ -138,7 +138,7 @@ nvkm_secboot_oneinit(struct nvkm_subdev *subdev)
case NVKM_SECBOOT_FALCON_SEC2:
/* we must keep SEC2 alive forever since ACR will run on it */
nvkm_engine_ref(&subdev->device->sec2->engine);
- sb->boot_falcon = subdev->device->sec2->falcon;
+ sb->boot_falcon = &subdev->device->sec2->falcon;
sb->halt_falcon = &subdev->device->pmu->falcon;
break;
default:
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c
index 472f38a56639..39dda09fc344 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c
@@ -148,7 +148,7 @@ acr_ls_ucode_load_sec2(const struct nvkm_secboot *sb, int maxver,
return ver;
/* Allocate the PMU queue corresponding to the FW version */
- ret = nvkm_msgqueue_new(img->ucode_desc.app_version, sec->falcon,
+ ret = nvkm_msgqueue_new(img->ucode_desc.app_version, &sec->falcon,
sb, &sec->queue);
if (ret)
return ret;
@@ -166,7 +166,7 @@ acr_ls_sec2_post_run(const struct nvkm_acr *acr, const struct nvkm_secboot *sb)
const u32 addr_args = 0x01000000;
int ret;
- ret = acr_ls_msgqueue_post_run(sec->queue, sec->falcon, addr_args);
+ ret = acr_ls_msgqueue_post_run(sec->queue, &sec->falcon, addr_args);
if (ret)
return ret;
--
2.28.0