From: Samuil Ivanov <samuil.ivanovbg@gmail.com>
Date: Wed, 23 Oct 2019 23:58:55 +0300
Subject: Staging: qlge: Rewrite two while loops as simple for loops
Patch-mainline: v5.5-rc1
Git-commit: 41e1bf811ace29bdc0df15523e3dfb3233704d1b
References: jsc#SLE-15139

This is a task from the TODO list of qlge driver:
 - some "while" loops could be rewritten with simple "for"

The change is in functions ql_wait_reg_rdy and ql_wait_cfg in qlge_main.c.
The while loops are basically count based
(they decrement on each iteration),
and it makes more sense to be a for loop construction instead.

Signed-off-by: Samuil Ivanov <samuil.ivanovbg@gmail.com>
Link: https://lore.kernel.org/r/20191023205855.GA1841@samuil-ThinkCentre-M92P
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
---
 drivers/staging/qlge/qlge_main.c |   10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

--- a/drivers/staging/qlge/qlge_main.c
+++ b/drivers/staging/qlge/qlge_main.c
@@ -167,9 +167,9 @@ void ql_sem_unlock(struct ql_adapter *qd
 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
 {
 	u32 temp;
-	int count = UDELAY_COUNT;
+	int count;
 
-	while (count) {
+	for (count = 0; count < UDELAY_COUNT; count++) {
 		temp = ql_read32(qdev, reg);
 
 		/* check for errors */
@@ -181,7 +181,6 @@ int ql_wait_reg_rdy(struct ql_adapter *q
 		} else if (temp & bit)
 			return 0;
 		udelay(UDELAY_DELAY);
-		count--;
 	}
 	netif_alert(qdev, probe, qdev->ndev,
 		    "Timed out waiting for reg %x to come ready.\n", reg);
@@ -193,17 +192,16 @@ int ql_wait_reg_rdy(struct ql_adapter *q
  */
 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
 {
-	int count = UDELAY_COUNT;
+	int count;
 	u32 temp;
 
-	while (count) {
+	for (count = 0; count < UDELAY_COUNT; count++) {
 		temp = ql_read32(qdev, CFG);
 		if (temp & CFG_LE)
 			return -EIO;
 		if (!(temp & bit))
 			return 0;
 		udelay(UDELAY_DELAY);
-		count--;
 	}
 	return -ETIMEDOUT;
 }