From: Michael Chan <michael.chan@broadcom.com>
Date: Mon, 4 May 2020 04:50:36 -0400
Subject: bnxt_en: Set the db_offset on 57500 chips for the RDMA MSIX entries.
Patch-mainline: v5.8-rc1
Git-commit: e93b30d56fc0670e508456afc59f16d70fe1f83f
References: jsc#SLE-15075

The driver provides completion ring or NQ doorbell offset for each
MSIX entry requested by the RDMA driver.  The NQ offset on 57500
chips is different than legacy chips.  Set it correctly based on
chip type for correctness.  The RDMA driver is ignoring this field
for the 57500 chips so it is not causing any problem.

Signed-off-by: Michael Chan <michael.chan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
---
 drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c |    8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c
@@ -104,7 +104,13 @@ static void bnxt_fill_msix_vecs(struct b
 	for (i = 0; i < num_msix; i++) {
 		ent[i].vector = bp->irq_tbl[idx + i].vector;
 		ent[i].ring_idx = idx + i;
-		ent[i].db_offset = (idx + i) * 0x80;
+		if (bp->flags & BNXT_FLAG_CHIP_P5) {
+			ent[i].db_offset = DB_PF_OFFSET_P5;
+			if (BNXT_VF(bp))
+				ent[i].db_offset = DB_VF_OFFSET_P5;
+		} else {
+			ent[i].db_offset = (idx + i) * 0x80;
+		}
 	}
 }