From: Jungseung Lee <js07.lee@samsung.com>
Date: Sat, 13 Jul 2019 22:56:20 +0900
Subject: mtd: spi-nor : Remove SPI_NOR_HAS_TB flag on s25fl512s
Git-commit: e7023898034ea3142661ecf02813177c00f3298c
Patch-mainline: v5.4-rc1
References: jsc#SLE-14214 jsc#SLE-16606
Currently, the Top/Bottom protection function (SPI_NOR_HAS_TB) is
implemented to fit some flashes with TB bit on SR.
s25fl512s has TBPROT bit on CR1, so the TB protection is not working on it.
Fix the wrong flag on s25fl512s.
Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
drivers/mtd/spi-nor/spi-nor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 4fb551aacd25..3790830d0d99 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2387,7 +2387,7 @@ static const struct flash_info spi_nor_ids[] = {
{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | USE_CLSR) },
+ SPI_NOR_HAS_LOCK | USE_CLSR) },
{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
--
2.28.0