From: Alexander Sverdlin <alexander.sverdlin@nokia.com>
Date: Fri, 12 Jul 2019 12:14:39 +0000
Subject: mtd: spi-nor: intel-spi: Whitelist 4B read commands
Git-commit: 913787ca40b9b5981bea1d1157cdd8cb23e12b54
Patch-mainline: v5.4-rc1
References: jsc#SLE-14214 jsc#SLE-16606
spi-nor.c issues 4B commands for some Flash chips bigger than 16Mbytes.
Xeon(R) D-1500 documentation mentions its Integrated PCH Logic supports
Flash chips up to 64Mbytes.
D-1500 Integrated PCH documenation however has inconsistencies regarding
FADDR register width and says nothing about particular commands issued
to support 64Mbytes of Flash.
Nevetheless the tests on Xeon(R) CPU D-1548 with 512Mbit Flash chips
Macronix MX25L51245G and Micron MT25QL512A showed that erase, write and
read operations work just fine after SPINOR_OP_READ_4B and
SPINOR_OP_READ_FAST_4B are white-listed (currently only
SPINOR_OP_READ_FAST_4B is used and only for Macronix).
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
drivers/mtd/spi-nor/intel-spi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c
index 1ccf23fe7e4b..43e55a2e9b27 100644
--- a/drivers/mtd/spi-nor/intel-spi.c
+++ b/drivers/mtd/spi-nor/intel-spi.c
@@ -621,6 +621,8 @@ static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len,
switch (nor->read_opcode) {
case SPINOR_OP_READ:
case SPINOR_OP_READ_FAST:
+ case SPINOR_OP_READ_4B:
+ case SPINOR_OP_READ_FAST_4B:
break;
default:
return -EINVAL;
--
2.28.0