From e5a4ab6a55e2308aad546b594c0d8e5b71d21be9 Mon Sep 17 00:00:00 2001
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Date: Mon, 13 Apr 2020 14:18:20 +0300
Subject: [PATCH] pinctrl: intel: Introduce common flags for GPIO mapping scheme
Git-commit: e5a4ab6a55e2308aad546b594c0d8e5b71d21be9
Patch-mainline: v5.8-rc1
References: jsc#SLE-12984
Few drivers are using the same flag to tell Intel pin control core
how to interpret GPIO base.
Provide a generic flags so all drivers can use.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Takashi Iwai <tiwai@suse.de>
---
drivers/pinctrl/intel/pinctrl-intel.c | 19 +++++++++++++------
drivers/pinctrl/intel/pinctrl-intel.h | 14 ++++++++++++--
2 files changed, 25 insertions(+), 8 deletions(-)
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -831,7 +831,7 @@ static int intel_gpio_to_pin(struct inte
for (j = 0; j < comm->ngpps; j++) {
const struct intel_padgroup *pgrp = &comm->gpps[j];
- if (pgrp->gpio_base < 0)
+ if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
continue;
if (offset >= pgrp->gpio_base &&
@@ -1168,7 +1168,7 @@ static int intel_gpio_add_pin_ranges(str
for (i = 0; i < community->ngpps; i++) {
const struct intel_padgroup *gpp = &community->gpps[i];
- if (gpp->gpio_base < 0)
+ if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
continue;
ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
@@ -1192,7 +1192,7 @@ static unsigned intel_gpio_ngpio(const s
for (j = 0; j < community->ngpps; j++) {
const struct intel_padgroup *gpp = &community->gpps[j];
- if (gpp->gpio_base < 0)
+ if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
continue;
if (gpp->gpio_base + gpp->size > ngpio)
@@ -1297,8 +1297,15 @@ static int intel_pinctrl_add_padgroups(s
if (gpps[i].size > 32)
return -EINVAL;
- if (!gpps[i].gpio_base)
- gpps[i].gpio_base = gpps[i].base;
+ /* Special treatment for GPIO base */
+ switch (gpps[i].gpio_base) {
+ case INTEL_GPIO_BASE_MATCH:
+ gpps[i].gpio_base = gpps[i].base;
+ break;
+ case INTEL_GPIO_BASE_NOMAP:
+ default:
+ break;
+ }
gpps[i].padown_num = padown_num;
@@ -1617,7 +1624,7 @@ static void intel_restore_hostown(struct
struct device *dev = pctrl->dev;
u32 requested;
- if (padgrp->gpio_base < 0)
+ if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
return;
requested = intel_gpio_is_requested(&pctrl->chip, padgrp->gpio_base, padgrp->size);
--- a/drivers/pinctrl/intel/pinctrl-intel.h
+++ b/drivers/pinctrl/intel/pinctrl-intel.h
@@ -50,8 +50,7 @@ struct intel_function {
* @reg_num: GPI_IS register number
* @base: Starting pin of this group
* @size: Size of this group (maximum is 32).
- * @gpio_base: Starting GPIO base of this group (%0 if matches with @base,
- * and %-1 if no GPIO mapping should be created)
+ * @gpio_base: Starting GPIO base of this group
* @padown_num: PAD_OWN register number (assigned by the core driver)
*
* If pad groups of a community are not the same size, use this structure
@@ -66,6 +65,17 @@ struct intel_padgroup {
};
/**
+ * enum - Special treatment for GPIO base in pad group
+ *
+ * @INTEL_GPIO_BASE_NOMAP: no GPIO mapping should be created
+ * @INTEL_GPIO_BASE_MATCH: matches with starting pin number
+ */
+enum {
+ INTEL_GPIO_BASE_NOMAP = -1,
+ INTEL_GPIO_BASE_MATCH = 0,
+};
+
+/**
* struct intel_community - Intel pin community description
* @barno: MMIO BAR number where registers for this community reside
* @padown_offset: Register offset of PAD_OWN register from @regs. If %0