From be08c52ec76a3b70093d7300bbcd906fc9ace78c Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Mon, 22 Jun 2020 20:18:06 +1000
Subject: drm/nouveau/fence: convert emit() to new push macros
Git-commit: 7aa638cfdb285946f989ac1e132e9c3378f26db6
Patch-mainline: v5.9-rc1
References: jsc#SLE-12680, jsc#SLE-12880, jsc#SLE-12882, jsc#SLE-12883, jsc#SLE-13496, jsc#SLE-15322
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/nouveau/nouveau_dma.h | 5 -----
drivers/gpu/drm/nouveau/nv04_fence.c | 11 +++++------
drivers/gpu/drm/nouveau/nv10_fence.c | 12 ++++++------
drivers/gpu/drm/nouveau/nv84_fence.c | 24 +++++++++++++-----------
drivers/gpu/drm/nouveau/nvc0_fence.c | 21 ++++++++++++---------
5 files changed, 36 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h
index 35318739f7f5..3e6c39d7ea01 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.h
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.h
@@ -45,11 +45,6 @@ void nv50_dma_push(struct nouveau_channel *, u64 addr, int length);
*/
#define NOUVEAU_DMA_SKIPS (128 / 4)
-/* Hardcoded object assignments to subchannels (subchannel id). */
-enum {
- NvSubSw = 1,
-};
-
/* Object handles - for stuff that's doesn't use handle == oclass. */
enum {
NvDmaFB = 0x80000002,
diff --git a/drivers/gpu/drm/nouveau/nv04_fence.c b/drivers/gpu/drm/nouveau/nv04_fence.c
index c41e82be4893..5b71a5a5cd85 100644
--- a/drivers/gpu/drm/nouveau/nv04_fence.c
+++ b/drivers/gpu/drm/nouveau/nv04_fence.c
@@ -21,12 +21,12 @@
*
* Authors: Ben Skeggs
*/
-
#include "nouveau_drv.h"
#include "nouveau_dma.h"
#include "nouveau_fence.h"
#include <nvif/if0004.h>
+#include <nvif/push006c.h>
struct nv04_fence_chan {
struct nouveau_fence_chan base;
@@ -39,12 +39,11 @@ struct nv04_fence_priv {
static int
nv04_fence_emit(struct nouveau_fence *fence)
{
- struct nouveau_channel *chan = fence->channel;
- int ret = RING_SPACE(chan, 2);
+ struct nvif_push *push = fence->channel->chan.push;
+ int ret = PUSH_WAIT(push, 2);
if (ret == 0) {
- BEGIN_NV04(chan, NvSubSw, 0x0150, 1);
- OUT_RING (chan, fence->base.seqno);
- FIRE_RING (chan);
+ PUSH_NVSQ(push, NV_SW, 0x0150, fence->base.seqno);
+ PUSH_KICK(push);
}
return ret;
}
diff --git a/drivers/gpu/drm/nouveau/nv10_fence.c b/drivers/gpu/drm/nouveau/nv10_fence.c
index 32d07f02b24c..b5117b0c71c1 100644
--- a/drivers/gpu/drm/nouveau/nv10_fence.c
+++ b/drivers/gpu/drm/nouveau/nv10_fence.c
@@ -21,20 +21,20 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
#include "nouveau_drv.h"
#include "nouveau_dma.h"
#include "nv10_fence.h"
+#include <nvif/push006c.h>
+
int
nv10_fence_emit(struct nouveau_fence *fence)
{
- struct nouveau_channel *chan = fence->channel;
- int ret = RING_SPACE(chan, 2);
+ struct nvif_push *push = fence->channel->chan.push;
+ int ret = PUSH_WAIT(push, 2);
if (ret == 0) {
- BEGIN_NV04(chan, 0, NV10_SUBCHAN_REF_CNT, 1);
- OUT_RING (chan, fence->base.seqno);
- FIRE_RING (chan);
+ PUSH_NVSQ(push, NV06E, NV10_SUBCHAN_REF_CNT, fence->base.seqno);
+ PUSH_KICK(push);
}
return ret;
}
diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c
index f07da00f285f..0c4b740abea8 100644
--- a/drivers/gpu/drm/nouveau/nv84_fence.c
+++ b/drivers/gpu/drm/nouveau/nv84_fence.c
@@ -21,7 +21,6 @@
*
* Authors: Ben Skeggs
*/
-
#include "nouveau_drv.h"
#include "nouveau_dma.h"
#include "nouveau_fence.h"
@@ -29,20 +28,23 @@
#include "nv50_display.h"
+#include <nvif/push206e.h>
+
static int
nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
{
- int ret = RING_SPACE(chan, 8);
+ struct nvif_push *push = chan->chan.push;
+ int ret = PUSH_WAIT(push, 8);
if (ret == 0) {
- BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
- OUT_RING (chan, chan->vram.handle);
- BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
- OUT_RING (chan, upper_32_bits(virtual));
- OUT_RING (chan, lower_32_bits(virtual));
- OUT_RING (chan, sequence);
- OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
- OUT_RING (chan, 0x00000000);
- FIRE_RING (chan);
+ PUSH_NVSQ(push, NV826F, NV11_SUBCHAN_DMA_SEMAPHORE, chan->vram.handle);
+ PUSH_NVSQ(push, NV826F,
+ NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual),
+ NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual),
+ NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence,
+ NV84_SUBCHAN_SEMAPHORE_TRIGGER,
+ NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG,
+ NV84_SUBCHAN_UEVENT, 0x00000000);
+ PUSH_KICK(push);
}
return ret;
}
diff --git a/drivers/gpu/drm/nouveau/nvc0_fence.c b/drivers/gpu/drm/nouveau/nvc0_fence.c
index b79775788bbd..e4b2efaee254 100644
--- a/drivers/gpu/drm/nouveau/nvc0_fence.c
+++ b/drivers/gpu/drm/nouveau/nvc0_fence.c
@@ -21,25 +21,28 @@
*
* Authors: Ben Skeggs
*/
-
#include "nouveau_drv.h"
#include "nouveau_dma.h"
#include "nouveau_fence.h"
#include "nv50_display.h"
+#include <nvif/push906f.h>
+
static int
nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
{
- int ret = RING_SPACE(chan, 6);
+ struct nvif_push *push = chan->chan.push;
+ int ret = PUSH_WAIT(push, 6);
if (ret == 0) {
- BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
- OUT_RING (chan, upper_32_bits(virtual));
- OUT_RING (chan, lower_32_bits(virtual));
- OUT_RING (chan, sequence);
- OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
- OUT_RING (chan, 0x00000000);
- FIRE_RING (chan);
+ PUSH_NVSQ(push, NV906F,
+ NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual),
+ NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual),
+ NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence,
+ NV84_SUBCHAN_SEMAPHORE_TRIGGER,
+ NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG,
+ NV84_SUBCHAN_UEVENT, 0x00000000);
+ PUSH_KICK(push);
}
return ret;
}
--
2.29.2