From 2c1746a1533835d003159851f3283338786492a5 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Sun, 21 Jun 2020 12:46:31 +1000
Subject: drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_or()
Git-commit: c854bf9464500d195f1a1a2c79ef887291b9300b
Patch-mainline: v5.9-rc1
References: jsc#SLE-12680, jsc#SLE-12880, jsc#SLE-12882, jsc#SLE-12883, jsc#SLE-13496, jsc#SLE-15322
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/nouveau/dispnv50/crc.c | 12 +++++-------
drivers/gpu/drm/nouveau/dispnv50/head907d.c | 15 ++++++++-------
drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 10 ++++++----
drivers/gpu/drm/nouveau/dispnv50/headc57d.c | 12 +++++++-----
4 files changed, 26 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc.c b/drivers/gpu/drm/nouveau/dispnv50/crc.c
index 4a43cca96328..b8c31b697797 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/crc.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/crc.c
@@ -9,6 +9,8 @@
#include <nvif/cl0002.h>
#include <nvif/timer.h>
+#include <nvhw/class/cl907d.h>
+
#include "nouveau_drv.h"
#include "core.h"
#include "head.h"
@@ -478,10 +480,6 @@ void nv50_crc_atomic_clr(struct nv50_head *head)
func->set_src(head, 0, NV50_CRC_SOURCE_TYPE_NONE, NULL, 0);
}
-#define NV50_CRC_RASTER_ACTIVE 0
-#define NV50_CRC_RASTER_COMPLETE 1
-#define NV50_CRC_RASTER_INACTIVE 2
-
static inline int
nv50_crc_raster_type(enum nv50_crc_source source)
{
@@ -490,11 +488,11 @@ nv50_crc_raster_type(enum nv50_crc_source source)
case NV50_CRC_SOURCE_AUTO:
case NV50_CRC_SOURCE_RG:
case NV50_CRC_SOURCE_OUTP_ACTIVE:
- return NV50_CRC_RASTER_ACTIVE;
+ return NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER;
case NV50_CRC_SOURCE_OUTP_COMPLETE:
- return NV50_CRC_RASTER_COMPLETE;
+ return NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER;
case NV50_CRC_SOURCE_OUTP_INACTIVE:
- return NV50_CRC_RASTER_INACTIVE;
+ return NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER;
}
return 0;
diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c
index 74f7901e953a..8f860e9c5224 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c
@@ -43,13 +43,14 @@ head907d_or(struct nv50_head *head, struct nv50_head_atom *asyh)
if ((ret = PUSH_WAIT(push, 3)))
return ret;
- PUSH_NVSQ(push, NV907D, 0x0404 + (i * 0x300), asyh->or.depth << 6 |
- asyh->or.nvsync << 4 |
- asyh->or.nhsync << 3 |
- asyh->or.crc_raster,
- 0x0408 + (i * 0x300), 0x31ec6000 |
- head->base.index << 25 |
- asyh->mode.interlace);
+ PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
+ NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, CRC_MODE, asyh->or.crc_raster) |
+ NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, HSYNC_POLARITY, asyh->or.nhsync) |
+ NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, VSYNC_POLARITY, asyh->or.nvsync) |
+ NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, PIXEL_DEPTH, asyh->or.depth),
+
+ HEAD_SET_CONTROL(i), 0x31ec6000 | head->base.index << 25 |
+ NVVAL(NV907D, HEAD_SET_CONTROL, STRUCTURE, asyh->mode.interlace));
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c
index ba2dc5a64a69..63adfeba50e5 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c
@@ -52,10 +52,12 @@ headc37d_or(struct nv50_head *head, struct nv50_head_atom *asyh)
if ((ret = PUSH_WAIT(push, 2)))
return ret;
- PUSH_NVSQ(push, NVC37D, 0x2004 + (i * 0x400), depth << 4 |
- asyh->or.nvsync << 3 |
- asyh->or.nhsync << 2 |
- asyh->or.crc_raster);
+ PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
+ NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, CRC_MODE, asyh->or.crc_raster) |
+ NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, HSYNC_POLARITY, asyh->or.nhsync) |
+ NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, VSYNC_POLARITY, asyh->or.nvsync) |
+ NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, PIXEL_DEPTH, depth) |
+ NVDEF(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, COLOR_SPACE_OVERRIDE, DISABLE));
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c
index 24c1cd2247c1..fd51527b56b8 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c
@@ -52,11 +52,13 @@ headc57d_or(struct nv50_head *head, struct nv50_head_atom *asyh)
if ((ret = PUSH_WAIT(push, 2)))
return ret;
- PUSH_NVSQ(push, NVC57D, 0x2004 + (i * 0x400), 0xfc000000 |
- depth << 4 |
- asyh->or.nvsync << 3 |
- asyh->or.nhsync << 2 |
- asyh->or.crc_raster);
+ PUSH_MTHD(push, NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
+ NVVAL(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, CRC_MODE, asyh->or.crc_raster) |
+ NVVAL(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, HSYNC_POLARITY, asyh->or.nhsync) |
+ NVVAL(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, VSYNC_POLARITY, asyh->or.nvsync) |
+ NVVAL(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, PIXEL_DEPTH, depth) |
+ NVDEF(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, COLOR_SPACE_OVERRIDE, DISABLE) |
+ NVDEF(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, EXT_PACKET_WIN, NONE));
return 0;
}
--
2.29.2