From 834185fbee9f7e42e2ce064e9847ae50a38e03f4 Mon Sep 17 00:00:00 2001
From: John Clements <john.clements@amd.com>
Date: Fri, 17 Jul 2020 14:13:50 +0800
Subject: drm/amdgpu: enable xgmi support for sienna cichlid
Git-commit: c652923afa7c8fef2aee42142e9663c0e69f367d
Patch-mainline: v5.9-rc1
References: jsc#SLE-12680, jsc#SLE-12880, jsc#SLE-12882, jsc#SLE-12883, jsc#SLE-13496, jsc#SLE-15322
set xgmi support flag suring nv ip init sequence
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 479991b71295..ea69ae76773e 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -446,6 +446,9 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
adev->nbio.funcs = &nbio_v2_3_funcs;
adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
+ if (adev->asic_type == CHIP_SIENNA_CICHLID)
+ adev->gmc.xgmi.supported = true;
+
/* Set IP register base before any HW register access */
r = nv_reg_base_init(adev);
if (r)
--
2.29.2