From 5cb4ca07c2d53d492f014ee65995fcfc08f43db9 Mon Sep 17 00:00:00 2001
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Date: Tue, 1 Oct 2019 11:01:00 -0400
Subject: drm/amd/display: fix number of dcn21 dpm clock levels
Git-commit: 5cb4ca07c2d53d492f014ee65995fcfc08f43db9
Patch-mainline: v5.5-rc1
References: bsc#1152472
These are specific to dcn21 and should not be increased for
reuse on other asics.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
---
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
index b01db61b6181..ef7df9ef6d7e 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
@@ -251,8 +251,8 @@ struct pp_smu_funcs_nv {
#define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8
#define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8
-#define PP_SMU_NUM_FCLK_DPM_LEVELS 8
-#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 8
+#define PP_SMU_NUM_FCLK_DPM_LEVELS 4
+#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 4
struct dpm_clock {
uint32_t Freq; // In MHz
--
2.28.0