From: Julien Grall <julien.grall@arm.com>
Date: Fri, 1 Nov 2019 15:20:22 +0000
Subject: docs/arm64: cpu-feature-registers: Rewrite bitfields that don't
follow [e, s]
Git-commit: 478016c3839d53bd4c89af1f095195be543fa1a3
Patch-mainline: v5.5-rc1
References: jsc#13705,jsc#13695
Commit "docs/arm64: cpu-feature-registers: Documents missing visible
fields" added bitfields following the convention [s, e]. However, the
documentation is following [s, e] and so does the Arm ARM.
Rewrite the bitfields to match the format [s, e].
Fixes: a8613e7070e7 ("docs/arm64: cpu-feature-registers: Documents missing visible fields")
Signed-off-by: Julien Grall <julien.grall@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
---
Documentation/arm64/cpu-feature-registers.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst
index ffcf4e2c71ef..7c40e4581bae 100644
--- a/Documentation/arm64/cpu-feature-registers.rst
+++ b/Documentation/arm64/cpu-feature-registers.rst
@@ -193,9 +193,9 @@ infrastructure:
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | SB | [36-39] | y |
+ | SB | [39-36] | y |
+------------------------------+---------+---------+
- | FRINTTS | [32-35] | y |
+ | FRINTTS | [35-32] | y |
+------------------------------+---------+---------+
| GPI | [31-28] | y |
+------------------------------+---------+---------+
--
2.26.2