From cac960c5912a7a63cbe77032b7b1cd60c3fee0d6 Mon Sep 17 00:00:00 2001
From: Heiner Kallweit <hkallweit1@gmail.com>
Date: Sat, 15 Feb 2020 14:48:49 +0100
Subject: [PATCH] r8169: remove setting PCI_CACHE_LINE_SIZE in rtl_hw_start_8169
Git-commit: cac960c5912a7a63cbe77032b7b1cd60c3fee0d6
Patch-mainline: v5.7-rc1
References: bsc#1175746
This is done for all RTL8169 chip versions in rtl8169_init_phy already.
Therefore we can remove it here.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Takashi Iwai <tiwai@suse.de>
---
drivers/net/ethernet/realtek/r8169_main.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
index b6614f15af0a..a9a55589ebd5 100644
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
@@ -3834,9 +3834,6 @@ static void rtl_hw_start_8168(struct rtl8169_private *tp)
static void rtl_hw_start_8169(struct rtl8169_private *tp)
{
- if (tp->mac_version == RTL_GIGA_MAC_VER_05)
- pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
-
RTL_W8(tp, EarlyTxThres, NoEarlyTx);
tp->cp_cmd |= PCIMulRW;
--
2.16.4