From: Thomas Gleixner <tglx@linutronix.de>
Date: Tue, 10 Nov 2020 15:34:32 +0100
Subject: x86/ioapic: Correct the PCI/ISA trigger type selection
Git-commit: aec8da04e4d71afdd4ab3025ea34a6517435f363
Patch-mainline: v5.11-rc1
References: jsc#SLE-16823
PCI's default trigger type is level and ISA's is edge. The recent
refactoring made it the other way round, which went unnoticed as it seems
only to cause havoc on some AMD systems.
Make the comment and code do the right thing again.
Fixes: a27dca645d2c ("x86/io_apic: Cleanup trigger/polarity helpers")
Reported-by: Tom Lendacky <thomas.lendacky@amd.com>
Reported-by: Borislav Petkov <bp@alien8.de>
Reported-by: Qian Cai <cai@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Tom Lendacky <thomas.lendacky@amd.com>
Cc: David Woodhouse <dwmw@amazon.co.uk>
Link: https://lore.kernel.org/r/87d00lgu13.fsf@nanos.tec.linutronix.de
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
---
arch/x86/kernel/apic/io_apic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -822,9 +822,9 @@ static bool irq_is_level(int idx)
case MP_IRQTRIG_DEFAULT:
/*
* Conforms to spec, ie. bus-type dependent trigger
- * mode. PCI defaults to egde, ISA to level.
+ * mode. PCI defaults to level, ISA to edge.
*/
- level = test_bit(bus, mp_bus_not_pci);
+ level = !test_bit(bus, mp_bus_not_pci);
/* Take EISA into account */
return eisa_irq_is_level(idx, bus, level);
case MP_IRQTRIG_EDGE: