From: Sinan Kaya <okaya@codeaurora.org>
Date: Thu, 19 Jul 2018 18:04:09 -0500
Subject: PCI: Handle error return from pci_reset_bridge_secondary_bus()
Patch-mainline: v4.19-rc1
Git-commit: 1842623850d09b0b1147d4974573aa305658d97f
References: bsc#1103992 FATE#326009
Commit 01fd61c0b9bd ("PCI: Add a return type for
pci_reset_bridge_secondary_bus()") added a return value to the function to
return if a device is accessible following a reset. Callers are not
checking the value.
Pass error code up high in the stack if device is not accessible.
Fixes: 01fd61c0b9bd ("PCI: Add a return type for pci_reset_bridge_secondary_bus()")
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
---
drivers/pci/hotplug/pciehp_hpc.c | 5 +++--
drivers/pci/pci.c | 12 ++++++------
drivers/pci/pcie/err.c | 6 ++++--
3 files changed, 13 insertions(+), 10 deletions(-)
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -735,6 +735,7 @@ int pciehp_reset_slot(struct slot *slot,
struct controller *ctrl = slot->ctrl;
struct pci_dev *pdev = ctrl_dev(ctrl);
u16 stat_mask = 0, ctrl_mask = 0;
+ int rc;
if (probe)
return 0;
@@ -752,7 +753,7 @@ int pciehp_reset_slot(struct slot *slot,
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
- pci_reset_bridge_secondary_bus(ctrl->pcie->port);
+ rc = pci_reset_bridge_secondary_bus(ctrl->pcie->port);
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
@@ -760,7 +761,7 @@ int pciehp_reset_slot(struct slot *slot,
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
up_write(&ctrl->reset_lock);
- return 0;
+ return rc;
}
int pcie_init_notification(struct controller *ctrl)
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4256,9 +4256,7 @@ static int pci_parent_bus_reset(struct p
if (probe)
return 0;
- pci_reset_bridge_secondary_bus(dev->bus->self);
-
- return 0;
+ return pci_reset_bridge_secondary_bus(dev->bus->self);
}
static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
@@ -4903,6 +4901,8 @@ EXPORT_SYMBOL_GPL(pci_try_reset_slot);
static int pci_bus_reset(struct pci_bus *bus, int probe)
{
+ int ret;
+
if (!bus->self || !pci_bus_resetable(bus))
return -ENOTTY;
@@ -4913,11 +4913,11 @@ static int pci_bus_reset(struct pci_bus
might_sleep();
- pci_reset_bridge_secondary_bus(bus->self);
+ ret = pci_reset_bridge_secondary_bus(bus->self);
pci_bus_unlock(bus);
- return 0;
+ return ret;
}
/**
@@ -4977,7 +4977,7 @@ int pci_try_reset_bus(struct pci_bus *bu
if (pci_bus_trylock(bus)) {
might_sleep();
- pci_reset_bridge_secondary_bus(bus->self);
+ rc = pci_reset_bridge_secondary_bus(bus->self);
pci_bus_unlock(bus);
} else
rc = -EAGAIN;
--- a/drivers/pci/pcie/err.c
+++ b/drivers/pci/pcie/err.c
@@ -175,9 +175,11 @@ out:
*/
static pci_ers_result_t default_reset_link(struct pci_dev *dev)
{
- pci_reset_bridge_secondary_bus(dev);
+ int rc;
+
+ rc = pci_reset_bridge_secondary_bus(dev);
pci_printk(KERN_DEBUG, dev, "downstream link has been reset\n");
- return PCI_ERS_RESULT_RECOVERED;
+ return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
}
static pci_ers_result_t reset_link(struct pci_dev *dev, u32 service)