From: Kan Liang <kan.liang@linux.intel.com>
Date: Wed, 30 Jun 2021 14:08:33 -0700
Subject: perf/x86/intel/uncore: Add Sapphire Rapids server UPI support
Git-commit: da5a9156cd2a3be2b00f8defb529ee3e35e5769b
Patch-mainline: v5.15-rc1
References: jsc#SLE-18939
Sapphire Rapids uses a coherent interconnect for scaling to multiple
sockets known as Intel UPI. Intel UPI technology provides a cache
coherent socket to socket external communication interface between
processors.
The layout of the control registers for a UPI uncore unit is similar to
a M2M uncore unit.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-10-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Tony Jones <tonyj@suse.de>
---
arch/x86/events/intel/uncore_snbep.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 72ba8d44d819..20045ba723b5 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -5698,6 +5698,11 @@ static struct intel_uncore_type spr_uncore_m2m = {
.name = "m2m",
};
+static struct intel_uncore_type spr_uncore_upi = {
+ SPR_UNCORE_PCI_COMMON_FORMAT(),
+ .name = "upi",
+};
+
#define UNCORE_SPR_NUM_UNCORE_TYPES 12
static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
@@ -5709,7 +5714,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
NULL,
&spr_uncore_imc,
&spr_uncore_m2m,
- NULL,
+ &spr_uncore_upi,
NULL,
NULL,
NULL,