From 06823925ad6b4fe14e652e3a386ac1472f371fa9 Mon Sep 17 00:00:00 2001
From: Xiaojie Yuan <xiaojie.yuan@amd.com>
Date: Mon, 17 Dec 2018 18:07:22 +0800
Subject: drm/amdgpu/sdma5: add placeholder for navi14 golden settings
Git-commit: 06823925ad6b4fe14e652e3a386ac1472f371fa9
Patch-mainline: v5.4-rc1
References: bsc#1152489

To be filled in once they are available.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 1be7f3e4d650..caf34dd3c573 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -85,6 +85,9 @@ static const struct soc15_reg_golden golden_settings_sdma_5[] = {
 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
 };
 
+static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
+};
+
 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
 {
 	u32 base;
@@ -114,6 +117,14 @@ static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
 						golden_settings_sdma_nv10,
 						(const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
 		break;
+	case CHIP_NAVI14:
+		soc15_program_register_sequence(adev,
+						golden_settings_sdma_5,
+						(const u32)ARRAY_SIZE(golden_settings_sdma_5));
+		soc15_program_register_sequence(adev,
+						golden_settings_sdma_nv14,
+						(const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
+		break;
 	default:
 		break;
 	}
-- 
2.28.0