From c52e7ebce72bc9d269c6025da5a4d41601e5f6ca Mon Sep 17 00:00:00 2001
From: Jonathan Kim <jonathan.kim@amd.com>
Date: Thu, 11 Jul 2019 12:19:44 -0400
Subject: drm/amdgpu: exposing fica registers to df offsets
Git-commit: c52e7ebce72bc9d269c6025da5a4d41601e5f6ca
Patch-mainline: v5.4-rc1
References: bsc#1152489
exposing fica registers to poll df pie data for xgmi error counters for
vega20.
Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
---
drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
index 6efcaa93e17b..c2bd25589e84 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
@@ -48,4 +48,8 @@
#define smnPerfMonCtrLo3 0x01d478UL
#define smnPerfMonCtrHi3 0x01d47cUL
+#define smnDF_PIE_AON_FabricIndirectConfigAccessAddress3 0x1d05cUL
+#define smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3 0x1d098UL
+#define smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3 0x1d09cUL
+
#endif
--
2.28.0