From 75c35000235f3662f2810e9a59b0c8eed045432e Mon Sep 17 00:00:00 2001
From: Nikola Cornij <nikola.cornij@amd.com>
Date: Wed, 19 Jun 2019 14:30:52 -0400
Subject: drm/amd/display: Power-gate all DSCs at driver init time
Git-commit: 75c35000235f3662f2810e9a59b0c8eed045432e
Patch-mainline: v5.4-rc1
References: bsc#1152489
[why]
DSC should be powered-on only on as-needed basis, i.e. if the mode
requires it
[how]
Loop over all the DSCs at driver init time and power-gate each
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index ddf15a3715e0..5ecf965bc3f5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -624,6 +624,10 @@ static void dcn20_init_hw(struct dc *dc)
}
}
+ /* Power gate DSCs */
+ for (i = 0; i < res_pool->res_cap->num_dsc; i++)
+ dcn20_dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
+
/* Blank pixel data with OPP DPG */
for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
struct timing_generator *tg = dc->res_pool->timing_generators[i];
--
2.28.0