From 1c074a63834e7414031f33c23efd87bbb8c25cea Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Thu, 25 Jul 2019 10:55:57 -0500
Subject: drm/amdgpu/powerplay: add set_mp1_state for vega12
Git-commit: 1c074a63834e7414031f33c23efd87bbb8c25cea
Patch-mainline: v5.4-rc1
References: bsc#1152489
This sets the SMU into the proper state for various
operations (shutdown, unload, GPU reset, etc.).
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
---
.../drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 26 ++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index efb6d3762feb..7af9ad450ac4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -2639,6 +2639,30 @@ static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_
return 0;
}
+static int vega12_set_mp1_state(struct pp_hwmgr *hwmgr,
+ enum pp_mp1_state mp1_state)
+{
+ uint16_t msg;
+ int ret;
+
+ switch (mp1_state) {
+ case PP_MP1_STATE_UNLOAD:
+ msg = PPSMC_MSG_PrepareMp1ForUnload;
+ break;
+ case PP_MP1_STATE_SHUTDOWN:
+ case PP_MP1_STATE_RESET:
+ case PP_MP1_STATE_NONE:
+ default:
+ return 0;
+ }
+
+ PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg)) == 0,
+ "[PrepareMp1] Failed!",
+ return ret);
+
+ return 0;
+}
+
static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
.backend_init = vega12_hwmgr_backend_init,
.backend_fini = vega12_hwmgr_backend_fini,
@@ -2695,7 +2719,7 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
.set_asic_baco_state = vega12_baco_set_state,
.get_ppfeature_status = vega12_get_ppfeature_status,
.set_ppfeature_status = vega12_set_ppfeature_status,
-
+ .set_mp1_state = vega12_set_mp1_state,
};
int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
--
2.28.0