From 8787ee01458f12959d2936af447e8af59b16f284 Mon Sep 17 00:00:00 2001
From: Huang Rui <ray.huang@amd.com>
Date: Wed, 24 Jul 2019 13:42:16 -0500
Subject: drm/amdgpu: add gmc v9 supports for renoir
Git-commit: 8787ee01458f12959d2936af447e8af59b16f284
Patch-mainline: v5.4-rc1
References: bsc#1152489
Add gfx memory controller support for renoir.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index e48fd19fd09c..040e4a68e0be 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -703,6 +703,7 @@ static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
case CHIP_VEGA10:
case CHIP_RAVEN:
case CHIP_ARCTURUS:
+ case CHIP_RENOIR:
return true;
case CHIP_VEGA12:
case CHIP_VEGA20:
@@ -1009,6 +1010,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
adev->gmc.gart_size = 512ULL << 20;
break;
case CHIP_RAVEN: /* DCE SG support */
+ case CHIP_RENOIR:
adev->gmc.gart_size = 1024ULL << 20;
break;
}
@@ -1059,6 +1061,7 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_RAVEN:
+ case CHIP_RENOIR:
viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
size = (REG_GET_FIELD(viewport,
HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
@@ -1115,8 +1118,10 @@ static int gmc_v9_0_sw_init(void *handle)
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
+ case CHIP_RENOIR:
adev->num_vmhubs = 2;
+
/*
* To fulfill 4-level page support,
* vm size is 256TB (48bit), maximum size of Vega10,
@@ -1288,6 +1293,7 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_VEGA12:
break;
case CHIP_RAVEN:
+ /* TODO for renoir */
soc15_program_register_sequence(adev,
golden_settings_athub_1_0_0,
ARRAY_SIZE(golden_settings_athub_1_0_0));
@@ -1322,6 +1328,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_RAVEN:
+ /* TODO for renoir */
mmhub_v1_0_update_power_gating(adev, true);
break;
default:
--
2.28.0