From 9d19c73f37473bfc4c9216e5e48b4684cc2050d2 Mon Sep 17 00:00:00 2001
From: Yongqiang Sun <yongqiang.sun@amd.com>
Date: Tue, 25 Jun 2019 19:08:50 -0400
Subject: drm/amd/display: Add DFS reference clock field
Git-commit: 9d19c73f37473bfc4c9216e5e48b4684cc2050d2
Patch-mainline: v5.4-rc1
References: bsc#1152489
Add to clk_mgr_internal struct, for future use.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
---
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index 4b5505fa980c..213046de1675 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -216,6 +216,8 @@ struct clk_mgr_internal {
bool dfs_bypass_enabled;
/* True if the DFS-bypass feature is enabled and active. */
bool dfs_bypass_active;
+
+ uint32_t dfs_ref_freq_khz;
/*
* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
* This is basically "Crystal Frequency In KHz" (XTALIN) frequency
--
2.28.0