From c43b849f890af2b638b3bea79a4203875bcc54d7 Mon Sep 17 00:00:00 2001
From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Date: Fri, 26 Jul 2019 14:07:42 -0400
Subject: drm/amdgpu: Use new mode2 reset interface for RV.
Git-commit: c43b849f890af2b638b3bea79a4203875bcc54d7
Patch-mainline: v5.4-rc1
References: bsc#1152489
Integrate the mode2 reset into rest sequence.
v2:
Check ppfuncs pointer for NULL
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/soc15.c | 25 +++++++++++++++-------
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1c4cfd7ba446..2f884699eaef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3525,6 +3525,7 @@ bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
case CHIP_VEGA20:
case CHIP_VEGA10:
case CHIP_VEGA12:
+ case CHIP_RAVEN:
break;
default:
goto disabled;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 2ccca8aafcaa..90a51490c6a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -509,6 +509,15 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
return 0;
}
+static int soc15_mode2_reset(struct amdgpu_device *adev)
+{
+ if (!adev->powerplay.pp_funcs ||
+ !adev->powerplay.pp_funcs->asic_reset_mode_2)
+ return -ENOENT;
+
+ return adev->powerplay.pp_funcs->asic_reset_mode_2(adev->powerplay.pp_handle);
+}
+
static enum amd_reset_method
soc15_asic_reset_method(struct amdgpu_device *adev)
{
@@ -547,14 +556,14 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
static int soc15_asic_reset(struct amdgpu_device *adev)
{
- int ret;
-
- if (soc15_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
- ret = soc15_asic_baco_reset(adev);
- else
- ret = soc15_asic_mode1_reset(adev);
-
- return ret;
+ switch (soc15_asic_reset_method(adev)) {
+ case AMD_RESET_METHOD_BACO:
+ return soc15_asic_baco_reset(adev);
+ case AMD_RESET_METHOD_MODE2:
+ return soc15_mode2_reset(adev);
+ default:
+ return soc15_asic_mode1_reset(adev);
+ }
}
/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
--
2.28.0