From da26ded3b2fff646d28559004195abe353bce49b Mon Sep 17 00:00:00 2001
From: YueHaibing <yuehaibing@huawei.com>
Date: Mon, 26 Aug 2019 16:57:07 +0800
Subject: drm/amdgpu/display: fix build error without
CONFIG_DRM_AMD_DC_DSC_SUPPORT
Git-commit: da26ded3b2fff646d28559004195abe353bce49b
Patch-mainline: v5.4-rc1
References: bsc#1152489
If CONFIG_DRM_AMD_DC_DSC_SUPPORT is not set, build fails:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c: In function dcn20_hw_sequencer_construct:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:2099:28:
error: dcn20_dsc_pg_control undeclared (first use in this function); did you mean dcn20_dpp_pg_control?
dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
^~~~~~~~~~~~~~~~~~~~
dcn20_dpp_pg_control
Use CONFIG_DRM_AMD_DC_DSC_SUPPORT to guard this.
Reported-by: Hulk Robot <hulkci@huawei.com>
Fixes: 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot")
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index d1c56fe9c301..1212da12c414 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2124,7 +2124,11 @@ void dcn20_hw_sequencer_construct(struct dc *dc)
dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane;
dc->hwss.dpp_pg_control = dcn20_dpp_pg_control;
dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
+#else
+ dc->hwss.dsc_pg_control = NULL;
+#endif
dc->hwss.disable_vga = dcn20_disable_vga;
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
--
2.28.0