From: Zhao Yan <yan.y.zhao@intel.com>
Date: Tue, 8 May 2018 14:52:42 +0800
Subject: drm/i915/gvt: do not return error on handling force_to_nonpriv
registers
Git-commit: 0438a1059877396319b90da289f1473c9c973cd8
Patch-mainline: v4.18-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
Return error will cause vm hang and enter failsafe mode.
However, we don't want that happen on detecting an wrong force_to_nonpriv
register write.
Therefore, we just omit the wrong write or patch it to default value.
v2: only return 0 on detecting lri write of registers outside whitelist,
but still return error on other error conditions. (zhenyu wang)
Signed-off-by: Zhao Yan <yan.y.zhao@intel.com>
Reviewed-by: Zhang Yulei <yulei.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 3 ++-
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -828,7 +828,8 @@ static int force_nonpriv_reg_handler(str
data != nopid) {
gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
offset, data);
- return -EPERM;
+ patch_value(s, cmd_ptr(s, index), nopid);
+ return 0;
}
return 0;
}
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -495,7 +495,7 @@ static int force_nonpriv_write(struct in
gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
vgpu->id, reg_nonpriv, offset);
- return ret;
+ return 0;
}
static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,