From 4739a9d2438bbc89e9aeea33b43680aeae2882e9 Mon Sep 17 00:00:00 2001
From: Imre Deak <imre.deak@intel.com>
Date: Mon, 6 Aug 2018 12:58:40 +0300
Subject: drm/i915: Remove redundant power well IDs
Git-commit: 4739a9d2438bbc89e9aeea33b43680aeae2882e9
Patch-mainline: v4.20-rc1
References: fate#326289
Now that we removed dependence on the power well IDs to determine the
control register and request/status flag offsets the only purpose of
power well IDs is to look up power wells directly bypassing the power
domains framework. However this direct lookup isn't needed for most of
the exisiting power wells and hopefully won't be needed for any new
power wells in the future. To make maintenance of the power well ID enum
easier, don't require a unique ID for each power well, only if it's
necessary. Remove the IDs becoming redundant this way and assign to all
the corresponding power wells a new DISP_PW_ID_NONE ID.
After the previous two patches the IDs don't need to have a fixed value,
so remove the explicit initializers and adjust the enum's code comment
accordingly.
v2:
- Keep required ID assignments for HSW_DISP_PW_GLOBAL and ICL_DISP_PW_2.
(Paulo)
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180806095843.13294-8-imre.deak@intel.com
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
---
drivers/gpu/drm/i915/i915_reg.h | 116 +++--------------------------
drivers/gpu/drm/i915/intel_runtime_pm.c | 127 ++++++++++++++++----------------
2 files changed, 77 insertions(+), 166 deletions(-)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1029,117 +1029,25 @@ static inline bool i915_mmio_reg_valid(i
/*
* i915_power_well_id:
*
- * Platform specific IDs used to look up power wells and - except for custom
- * power wells - to define request/status register flag bit positions. As such
- * the set of IDs on a given platform must be unique and except for custom
- * power wells their value must stay fixed.
+ * IDs used to look up power wells. Power wells accessed directly bypassing
+ * the power domains framework must be assigned a unique ID. The rest of power
+ * wells must be assigned DISP_PW_ID_NONE.
*/
enum i915_power_well_id {
- /*
- * I830
- * - custom power well
- */
- I830_DISP_PW_PIPES = 0,
+ DISP_PW_ID_NONE,
- /*
- * VLV/CHV
- * - PUNIT_REG_PWRGT_CTRL (bit: id*2),
- * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8)
- */
- PUNIT_POWER_WELL_RENDER = 0,
- PUNIT_POWER_WELL_MEDIA = 1,
- PUNIT_POWER_WELL_DISP2D = 3,
- PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
- PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
- PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
- PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
- PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
- PUNIT_POWER_WELL_DPIO_RX0 = 10,
- PUNIT_POWER_WELL_DPIO_RX1 = 11,
- PUNIT_POWER_WELL_DPIO_CMN_D = 12,
- /* - custom power well */
- CHV_DISP_PW_PIPE_A, /* 13 */
-
- /*
- * HSW/BDW
- * - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit: id*2+1)
- */
- HSW_DISP_PW_GLOBAL = 15,
-
- /*
- * GEN9+
- * - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit: id*2+1)
- */
- SKL_DISP_PW_MISC_IO = 0,
- SKL_DISP_PW_DDI_A_E,
- GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
- CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
- SKL_DISP_PW_DDI_B,
- SKL_DISP_PW_DDI_C,
- SKL_DISP_PW_DDI_D,
- CNL_DISP_PW_DDI_F = 6,
-
- GLK_DISP_PW_AUX_A = 8,
- GLK_DISP_PW_AUX_B,
- GLK_DISP_PW_AUX_C,
- CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A,
- CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
- CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
- CNL_DISP_PW_AUX_D,
- CNL_DISP_PW_AUX_F,
-
- SKL_DISP_PW_1 = 14,
+ PUNIT_POWER_WELL_DISP2D,
+ PUNIT_POWER_WELL_DPIO_CMN_BC,
+ PUNIT_POWER_WELL_DPIO_CMN_D,
+ HSW_DISP_PW_GLOBAL,
+ SKL_DISP_PW_MISC_IO,
+ SKL_DISP_PW_1,
SKL_DISP_PW_2,
-
- /* - custom power wells */
BXT_DPIO_CMN_A,
BXT_DPIO_CMN_BC,
- GLK_DPIO_CMN_C, /* 18 */
-
- /*
- * GEN11+
- * - _HSW_PWR_WELL_CTL1-4
- * (status bit: (id&15)*2, req bit:(id&15)*2+1)
- */
- ICL_DISP_PW_1 = 0,
+ GLK_DPIO_CMN_C,
+ ICL_DISP_PW_1,
ICL_DISP_PW_2,
- ICL_DISP_PW_3,
- ICL_DISP_PW_4,
-
- /*
- * - _HSW_PWR_WELL_CTL_AUX1/2/4
- * (status bit: (id&15)*2, req bit:(id&15)*2+1)
- */
- ICL_DISP_PW_AUX_A = 16,
- ICL_DISP_PW_AUX_B,
- ICL_DISP_PW_AUX_C,
- ICL_DISP_PW_AUX_D,
- ICL_DISP_PW_AUX_E,
- ICL_DISP_PW_AUX_F,
-
- ICL_DISP_PW_AUX_TBT1 = 24,
- ICL_DISP_PW_AUX_TBT2,
- ICL_DISP_PW_AUX_TBT3,
- ICL_DISP_PW_AUX_TBT4,
-
- /*
- * - _HSW_PWR_WELL_CTL_DDI1/2/4
- * (status bit: (id&15)*2, req bit:(id&15)*2+1)
- */
- ICL_DISP_PW_DDI_A = 32,
- ICL_DISP_PW_DDI_B,
- ICL_DISP_PW_DDI_C,
- ICL_DISP_PW_DDI_D,
- ICL_DISP_PW_DDI_E,
- ICL_DISP_PW_DDI_F, /* 37 */
-
- /*
- * Multiple platforms.
- * Must start following the highest ID of any platform.
- * - custom power wells
- */
- SKL_DISP_PW_DC_OFF = 38,
- I915_DISP_PW_ALWAYS_ON,
};
#define PUNIT_REG_PWRGT_CTRL 0x60
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1523,7 +1523,7 @@ out:
static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A);
+ WARN_ON_ONCE(power_well->id != DISP_PW_ID_NONE);
chv_set_pipe_power_well(dev_priv, power_well, true);
@@ -1533,7 +1533,7 @@ static void chv_pipe_power_well_enable(s
static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A);
+ WARN_ON_ONCE(power_well->id != DISP_PW_ID_NONE);
vlv_display_power_well_deinit(dev_priv);
@@ -2076,7 +2076,7 @@ static struct i915_power_well i9xx_alway
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
};
@@ -2093,13 +2093,13 @@ static struct i915_power_well i830_power
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "pipes",
.domains = I830_PIPES_POWER_DOMAINS,
.ops = &i830_pipes_power_well_ops,
- .id = I830_DISP_PW_PIPES,
+ .id = DISP_PW_ID_NONE,
},
};
@@ -2137,7 +2137,7 @@ static struct i915_power_well hsw_power_
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "display",
@@ -2158,7 +2158,7 @@ static struct i915_power_well bdw_power_
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "display",
@@ -2201,7 +2201,7 @@ static struct i915_power_well vlv_power_
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "display",
@@ -2219,7 +2219,7 @@ static struct i915_power_well vlv_power_
VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
- .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
+ .id = DISP_PW_ID_NONE,
{
.vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
},
@@ -2231,7 +2231,7 @@ static struct i915_power_well vlv_power_
VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
- .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
+ .id = DISP_PW_ID_NONE,
{
.vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
},
@@ -2243,7 +2243,7 @@ static struct i915_power_well vlv_power_
VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
- .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
+ .id = DISP_PW_ID_NONE,
{
.vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
},
@@ -2255,7 +2255,7 @@ static struct i915_power_well vlv_power_
VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
- .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
+ .id = DISP_PW_ID_NONE,
{
.vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
},
@@ -2277,7 +2277,7 @@ static struct i915_power_well chv_power_
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "display",
@@ -2288,7 +2288,7 @@ static struct i915_power_well chv_power_
*/
.domains = CHV_DISPLAY_POWER_DOMAINS,
.ops = &chv_pipe_power_well_ops,
- .id = CHV_DISP_PW_PIPE_A,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "dpio-common-bc",
@@ -2328,7 +2328,7 @@ static struct i915_power_well skl_power_
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 1",
@@ -2357,7 +2357,7 @@ static struct i915_power_well skl_power_
.name = "DC off",
.domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_PW_DC_OFF,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 2",
@@ -2376,7 +2376,7 @@ static struct i915_power_well skl_power_
.name = "DDI A/E IO power well",
.domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_A_E,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
@@ -2386,7 +2386,7 @@ static struct i915_power_well skl_power_
.name = "DDI B IO power well",
.domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_B,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
@@ -2396,7 +2396,7 @@ static struct i915_power_well skl_power_
.name = "DDI C IO power well",
.domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_C,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_C,
@@ -2406,7 +2406,7 @@ static struct i915_power_well skl_power_
.name = "DDI D IO power well",
.domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_D,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_D,
@@ -2420,7 +2420,7 @@ static struct i915_power_well bxt_power_
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 1",
@@ -2437,7 +2437,7 @@ static struct i915_power_well bxt_power_
.name = "DC off",
.domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_PW_DC_OFF,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 2",
@@ -2478,7 +2478,7 @@ static struct i915_power_well glk_power_
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 1",
@@ -2496,7 +2496,7 @@ static struct i915_power_well glk_power_
.name = "DC off",
.domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_PW_DC_OFF,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 2",
@@ -2542,7 +2542,7 @@ static struct i915_power_well glk_power_
.name = "AUX A",
.domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = GLK_DISP_PW_AUX_A,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_AUX_A,
@@ -2552,7 +2552,7 @@ static struct i915_power_well glk_power_
.name = "AUX B",
.domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = GLK_DISP_PW_AUX_B,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_AUX_B,
@@ -2562,7 +2562,7 @@ static struct i915_power_well glk_power_
.name = "AUX C",
.domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = GLK_DISP_PW_AUX_C,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_AUX_C,
@@ -2572,7 +2572,7 @@ static struct i915_power_well glk_power_
.name = "DDI A IO power well",
.domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = GLK_DISP_PW_DDI_A,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_DDI_A,
@@ -2582,7 +2582,7 @@ static struct i915_power_well glk_power_
.name = "DDI B IO power well",
.domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_B,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
@@ -2592,7 +2592,7 @@ static struct i915_power_well glk_power_
.name = "DDI C IO power well",
.domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_C,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_C,
@@ -2606,7 +2606,7 @@ static struct i915_power_well cnl_power_
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 1",
@@ -2624,7 +2624,7 @@ static struct i915_power_well cnl_power_
.name = "AUX A",
.domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_A,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_AUX_A,
@@ -2634,7 +2634,7 @@ static struct i915_power_well cnl_power_
.name = "AUX B",
.domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_B,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_AUX_B,
@@ -2644,7 +2644,7 @@ static struct i915_power_well cnl_power_
.name = "AUX C",
.domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_C,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_AUX_C,
@@ -2654,7 +2654,7 @@ static struct i915_power_well cnl_power_
.name = "AUX D",
.domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_D,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = CNL_PW_CTL_IDX_AUX_D,
@@ -2664,7 +2664,7 @@ static struct i915_power_well cnl_power_
.name = "DC off",
.domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_PW_DC_OFF,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 2",
@@ -2683,7 +2683,7 @@ static struct i915_power_well cnl_power_
.name = "DDI A IO power well",
.domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_DDI_A,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_DDI_A,
@@ -2693,7 +2693,7 @@ static struct i915_power_well cnl_power_
.name = "DDI B IO power well",
.domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_B,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
@@ -2703,7 +2703,7 @@ static struct i915_power_well cnl_power_
.name = "DDI C IO power well",
.domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_C,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_C,
@@ -2713,7 +2713,7 @@ static struct i915_power_well cnl_power_
.name = "DDI D IO power well",
.domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_D,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_D,
@@ -2723,7 +2723,7 @@ static struct i915_power_well cnl_power_
.name = "DDI F IO power well",
.domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_DDI_F,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = CNL_PW_CTL_IDX_DDI_F,
@@ -2733,7 +2733,7 @@ static struct i915_power_well cnl_power_
.name = "AUX F",
.domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_F,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = CNL_PW_CTL_IDX_AUX_F,
@@ -2766,7 +2766,7 @@ static struct i915_power_well icl_power_
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 1",
@@ -2795,13 +2795,13 @@ static struct i915_power_well icl_power_
.name = "DC off",
.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_PW_DC_OFF,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 3",
.domains = ICL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_3,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
@@ -2814,7 +2814,7 @@ static struct i915_power_well icl_power_
.name = "DDI A IO",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_DDI_A,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
@@ -2824,7 +2824,7 @@ static struct i915_power_well icl_power_
.name = "DDI B IO",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_DDI_B,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
@@ -2834,7 +2834,7 @@ static struct i915_power_well icl_power_
.name = "DDI C IO",
.domains = ICL_DDI_IO_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_DDI_C,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
@@ -2844,7 +2844,7 @@ static struct i915_power_well icl_power_
.name = "DDI D IO",
.domains = ICL_DDI_IO_D_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_DDI_D,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_D,
@@ -2854,7 +2854,7 @@ static struct i915_power_well icl_power_
.name = "DDI E IO",
.domains = ICL_DDI_IO_E_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_DDI_E,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_E,
@@ -2864,7 +2864,7 @@ static struct i915_power_well icl_power_
.name = "DDI F IO",
.domains = ICL_DDI_IO_F_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_DDI_F,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_F,
@@ -2874,7 +2874,7 @@ static struct i915_power_well icl_power_
.name = "AUX A",
.domains = ICL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_combo_phy_aux_power_well_ops,
- .id = ICL_DISP_PW_AUX_A,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
@@ -2884,7 +2884,7 @@ static struct i915_power_well icl_power_
.name = "AUX B",
.domains = ICL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_combo_phy_aux_power_well_ops,
- .id = ICL_DISP_PW_AUX_B,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
@@ -2894,7 +2894,7 @@ static struct i915_power_well icl_power_
.name = "AUX C",
.domains = ICL_AUX_C_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_AUX_C,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
@@ -2904,7 +2904,7 @@ static struct i915_power_well icl_power_
.name = "AUX D",
.domains = ICL_AUX_D_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_AUX_D,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_D,
@@ -2914,7 +2914,7 @@ static struct i915_power_well icl_power_
.name = "AUX E",
.domains = ICL_AUX_E_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_AUX_E,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_E,
@@ -2924,7 +2924,7 @@ static struct i915_power_well icl_power_
.name = "AUX F",
.domains = ICL_AUX_F_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_AUX_F,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_F,
@@ -2934,7 +2934,7 @@ static struct i915_power_well icl_power_
.name = "AUX TBT1",
.domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_AUX_TBT1,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
@@ -2944,7 +2944,7 @@ static struct i915_power_well icl_power_
.name = "AUX TBT2",
.domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_AUX_TBT2,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
@@ -2954,7 +2954,7 @@ static struct i915_power_well icl_power_
.name = "AUX TBT3",
.domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_AUX_TBT3,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
@@ -2964,7 +2964,7 @@ static struct i915_power_well icl_power_
.name = "AUX TBT4",
.domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_AUX_TBT4,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
@@ -2974,7 +2974,7 @@ static struct i915_power_well icl_power_
.name = "power well 4",
.domains = ICL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_4,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
@@ -3053,6 +3053,9 @@ static void assert_power_well_ids_unique
for (i = 0; i < power_domains->power_well_count; i++) {
enum i915_power_well_id id = power_domains->power_wells[i].id;
+ if (id == DISP_PW_ID_NONE)
+ continue;
+
WARN_ON(id >= sizeof(power_well_ids) * 8);
WARN_ON(power_well_ids & BIT_ULL(id));
power_well_ids |= BIT_ULL(id);