From 39947afc6c063940cbd80824e75eb0cf84591c3c Mon Sep 17 00:00:00 2001
From: Yan Zhao <yan.y.zhao@intel.com>
Date: Tue, 7 May 2019 22:15:00 -0400
Subject: drm/i915/gvt: Tiled Resources mmios are in-context mmios for gen9+
Git-commit: 39947afc6c063940cbd80824e75eb0cf84591c3c
Patch-mainline: v5.2-rc2
References: bsc#1113722

TRVATTL3PTRDW(0x4de0-0x4de4), TRNULLDETCT(0x4de8), TRINVTILEDETCT(0x4dec),
TRTTE(0x4df0), TRVADR(0x4df4) are in-context mmios for gen9+

Fixes: 178657139307 ("drm/i915/gvt: vGPU context switch")
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Yan Zhao <yan.y.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
---
 drivers/gpu/drm/i915/gvt/mmio_context.c |   12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -119,12 +119,12 @@ static struct engine_mmio gen9_engine_mm
 	{RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
 	{RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
 	{RCS, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
-	{RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */
-	{RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */
-	{RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */
-	{RCS, TRINVTILEDETCT, 0, false}, /* 0x4dec */
-	{RCS, TRVADR, 0, false}, /* 0x4df0 */
-	{RCS, TRTTE, 0, false}, /* 0x4df4 */
+	{RCS, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */
+	{RCS, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */
+	{RCS, TRNULLDETCT, 0, true}, /* 0x4de8 */
+	{RCS, TRINVTILEDETCT, 0, true}, /* 0x4dec */
+	{RCS, TRVADR, 0, true}, /* 0x4df0 */
+	{RCS, TRTTE, 0, true}, /* 0x4df4 */
 
 	{BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
 	{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */