From: Leo Liu <leo.liu@amd.com>
Date: Tue, 7 Feb 2017 11:47:12 -0500
Subject: drm/amdgpu: expose vcn RB command
Git-commit: 7741cced67aed83d87152a601d58bfb16eda8301
Patch-mainline: v4.13-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |    7 +++++++
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   |    8 ++++----
 2 files changed, 11 insertions(+), 4 deletions(-)

--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -30,6 +30,13 @@
 #define AMDGPU_VCN_FIRMWARE_OFFSET	256
 #define AMDGPU_VCN_MAX_ENC_RINGS	3
 
+#define VCN_CMD_FENCE			0x00000000
+#define VCN_CMD_TRAP			0x00000001
+#define VCN_CMD_WRITE_REG		0x00000004
+#define VCN_CMD_REG_READ_COND_WAIT	0x00000006
+#define VCN_CMD_PACKET_START		0x0000000a
+#define VCN_CMD_PACKET_END		0x0000000b
+
 struct amdgpu_vcn {
 	struct amdgpu_bo	*vcpu_bo;
 	void			*cpu_addr;
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -512,7 +512,7 @@ static void vcn_v1_0_dec_ring_emit_fence
 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 	amdgpu_ring_write(ring,
 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
-	amdgpu_ring_write(ring, 0);
+	amdgpu_ring_write(ring, VCN_CMD_FENCE << 1);
 
 	amdgpu_ring_write(ring,
 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
@@ -522,7 +522,7 @@ static void vcn_v1_0_dec_ring_emit_fence
 	amdgpu_ring_write(ring, 0);
 	amdgpu_ring_write(ring,
 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
-	amdgpu_ring_write(ring, 2);
+	amdgpu_ring_write(ring, VCN_CMD_TRAP << 1);
 }
 
 /**
@@ -576,7 +576,7 @@ static void vcn_v1_0_dec_vm_reg_write(st
 	amdgpu_ring_write(ring, data1);
 	amdgpu_ring_write(ring,
 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
-	amdgpu_ring_write(ring, 8);
+	amdgpu_ring_write(ring, VCN_CMD_WRITE_REG << 1);
 }
 
 static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring,
@@ -593,7 +593,7 @@ static void vcn_v1_0_dec_vm_reg_wait(str
 	amdgpu_ring_write(ring, mask);
 	amdgpu_ring_write(ring,
 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
-	amdgpu_ring_write(ring, 12);
+	amdgpu_ring_write(ring, VCN_CMD_REG_READ_COND_WAIT << 1);
 }
 
 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,