From: Felix Kuehling <Felix.Kuehling@amd.com>
Date: Mon, 15 May 2017 04:08:28 -0400
Subject: drm/amd/powerplay: Fix Vega10 power profile switching
Git-commit: e0ec45063609b4a583e7f4d843275888f2480321
Patch-mainline: v4.13-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

Clock index 0 is a valid index that is needed to restore the default
graphics power profile. Use ~0 to indicate a failure to find a clock
index. This fixes the clocks getting stuck in the compute power
profile after running a compute application on Vega10.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4584,7 +4584,7 @@ static int vega10_set_power_profile_stat
 		struct amd_pp_profile *request)
 {
 	struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
-	uint32_t sclk_idx = 0, mclk_idx = 0;
+	uint32_t sclk_idx = ~0, mclk_idx = ~0;
 
 	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO)
 		return -EINVAL;
@@ -4592,7 +4592,7 @@ static int vega10_set_power_profile_stat
 	vega10_find_min_clock_index(hwmgr, &sclk_idx, &mclk_idx,
 			request->min_sclk, request->min_mclk);
 
-	if (sclk_idx) {
+	if (sclk_idx != ~0) {
 		if (!data->registry_data.sclk_dpm_key_disabled)
 			PP_ASSERT_WITH_CODE(
 					!smum_send_msg_to_smc_with_parameter(
@@ -4603,7 +4603,7 @@ static int vega10_set_power_profile_stat
 					return -EINVAL);
 	}
 
-	if (mclk_idx) {
+	if (mclk_idx != ~0) {
 		if (!data->registry_data.mclk_dpm_key_disabled)
 			PP_ASSERT_WITH_CODE(
 					!smum_send_msg_to_smc_with_parameter(