From: Rex Zhu <Rex.Zhu@amd.com>
Date: Fri, 2 Jun 2017 20:04:40 +0800
Subject: drm/amd/powerplay: fix populate dpm level failed when s3 on vega10.
Git-commit: d0856f3ad5af1e2487df97fa667307982c89b717
Patch-mainline: v4.13-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
As the min clk may be large than boot level can support.
in this case, just ignore the min clk.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3120,11 +3120,10 @@ static int vega10_apply_state_adjust_rul
vega10_ps->performance_levels[0].gfx_clock = sclk;
vega10_ps->performance_levels[0].mem_clock = mclk;
- vega10_ps->performance_levels[1].gfx_clock =
- (vega10_ps->performance_levels[1].gfx_clock >=
- vega10_ps->performance_levels[0].gfx_clock) ?
- vega10_ps->performance_levels[1].gfx_clock :
- vega10_ps->performance_levels[0].gfx_clock;
+ if (vega10_ps->performance_levels[1].gfx_clock <
+ vega10_ps->performance_levels[0].gfx_clock)
+ vega10_ps->performance_levels[0].gfx_clock =
+ vega10_ps->performance_levels[1].gfx_clock;
if (disable_mclk_switching) {
/* Set Mclk the max of level 0 and level 1 */
@@ -3147,8 +3146,8 @@ static int vega10_apply_state_adjust_rul
} else {
if (vega10_ps->performance_levels[1].mem_clock <
vega10_ps->performance_levels[0].mem_clock)
- vega10_ps->performance_levels[1].mem_clock =
- vega10_ps->performance_levels[0].mem_clock;
+ vega10_ps->performance_levels[0].mem_clock =
+ vega10_ps->performance_levels[1].mem_clock;
}
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,