From: Jordan Lazare <Jordan.Lazare@amd.com>
Date: Wed, 14 Dec 2016 15:35:13 -0500
Subject: drm/amd/dal: Add POLARIS12 support (v2)
Git-commit: b264d3455d9c8ce0bea422a04a867f0a724c7770
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
v2: agd: squash in dm fix, rebase
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 3 ++-
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 5 ++++-
4 files changed, 10 insertions(+), 3 deletions(-)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1235,6 +1235,7 @@ int amdgpu_dm_initialize_drm_device(stru
case CHIP_STONEY:
case CHIP_POLARIS11:
case CHIP_POLARIS10:
+ case CHIP_POLARIS12:
if (dce110_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
return -1;
@@ -1472,6 +1473,7 @@ static int dm_early_init(void *handle)
adev->mode_info.num_dig = 9;
break;
case CHIP_POLARIS11:
+ case CHIP_POLARIS12:
adev->mode_info.num_crtc = 5;
adev->mode_info.num_hpd = 5;
adev->mode_info.num_dig = 5;
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -60,7 +60,8 @@ enum dce_version resource_parse_asic_id(
break;
}
if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
- ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev)) {
+ ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
+ ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
dc_version = DCE_VERSION_11_2;
}
break;
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -1233,7 +1233,8 @@ static void bw_calcs_data_update_from_pp
const struct resource_caps *dce112_resource_cap(
struct hw_asic_id *asic_id)
{
- if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev))
+ if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||
+ ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev))
return &polaris_11_resource_cap;
else
return &polaris_10_resource_cap;
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -85,6 +85,7 @@
/* DCE112 */
#define VI_POLARIS10_P_A0 80
#define VI_POLARIS11_M_A0 90
+#define VI_POLARIS12_V_A0 100
#define VI_UNKNOWN 0xFF
@@ -95,7 +96,9 @@
#define ASIC_REV_IS_POLARIS10_P(eChipRev) ((eChipRev >= VI_POLARIS10_P_A0) && \
(eChipRev < VI_POLARIS11_M_A0))
-#define ASIC_REV_IS_POLARIS11_M(eChipRev) (eChipRev >= VI_POLARIS11_M_A0)
+#define ASIC_REV_IS_POLARIS11_M(eChipRev) ((eChipRev >= VI_POLARIS11_M_A0) && \
+ (eChipRev < VI_POLARIS12_V_A0))
+#define ASIC_REV_IS_POLARIS12_V(eChipRev) (eChipRev >= VI_POLARIS12_V_A0)
/* DCE11 */
#define CZ_CARRIZO_A0 0x01