From: Zeyu Fan <Zeyu.Fan@amd.com>
Date: Fri, 10 Feb 2017 11:59:31 -0500
Subject: drm/amd/display: Fix program pix clk logic to unblock deep color set.
Git-commit: 27e947b0e13835cb782aa267b7d77e1f5a028e87
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c |   10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -854,16 +854,16 @@ static bool dce110_program_pix_clk(
 		if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL
 			&& pix_clk_params->flags.ENABLE_SS && !dc_is_dp_signal(
 							pix_clk_params->signal_type)) {
-
 			if (!enable_spread_spectrum(clk_src,
 							pix_clk_params->signal_type,
 							pll_settings))
 				return false;
-			/* Resync deep color DTO */
-			dce110_program_pixel_clk_resync(clk_src,
-						pix_clk_params->signal_type,
-						pix_clk_params->color_depth);
 		}
+		/* Resync deep color DTO */
+		dce110_program_pixel_clk_resync(clk_src,
+					pix_clk_params->signal_type,
+					pix_clk_params->color_depth);
+
 		break;
 	case DCE_VERSION_11_2:
 		if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {