From: Harry Wentland <harry.wentland@amd.com>
Date: Fri, 5 May 2017 14:57:12 -0400
Subject: drm/amd/display: DCE12 num_timing_generators should be 6
Git-commit: 6a4c32dac559a90b83c5f268b02c1a94df411159
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

We should also use it to determine pipe count.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -426,7 +426,7 @@ static const struct bios_registers bios_
 };
 
 static const struct resource_caps res_cap = {
-		.num_timing_generator = 3,
+		.num_timing_generator = 6,
 		.num_audio = 7,
 		.num_stream_encoder = 6,
 		.num_pll = 6,
@@ -909,7 +909,7 @@ static bool construct(
 	pool->base.funcs = &dce120_res_pool_funcs;
 
 	/* TODO: Fill more data from GreenlandAsicCapability.cpp */
-	pool->base.pipe_count = 6;
+	pool->base.pipe_count = res_cap.num_timing_generator;
 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 
 	dc->public.caps.max_downscale_ratio = 200;