From: Charlene Liu <charlene.liu@amd.com>
Date: Mon, 21 Aug 2017 12:59:41 -0400
Subject: drm/amd/display: write dpcd 0x600 to 2 for DP/eDP when powerdown
Git-commit: a0c38ebaa1fe99ea8d112d808d84a2e75194fcf6
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c               |    2 +-
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c |   10 +++++++++-
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h |    1 +
 3 files changed, 11 insertions(+), 2 deletions(-)

--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1977,7 +1977,7 @@ bool dc_link_setup_psr(struct dc_link *l
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 		/*skip power down the single pipe since it blocks the cstate*/
 		if (ASIC_REV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
-			psr_context->psr_level.bits.SKIP_SINGLE_OTG_DISABLE = false;
+			psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
 #endif
 
 		/* SMU will perform additional powerdown sequence.
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1147,8 +1147,16 @@ static enum dc_status apply_single_contr
 static void power_down_encoders(struct dc *dc)
 {
 	int i;
-
+	enum connector_id connector_id;
 	for (i = 0; i < dc->link_count; i++) {
+		connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
+		if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
+			(connector_id == CONNECTOR_ID_EDP)) {
+
+			if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
+				dp_receiver_power_ctrl(dc->links[i], false);
+		}
+
 		dc->links[i]->link_enc->funcs->disable_output(
 				dc->links[i]->link_enc, SIGNAL_TYPE_NONE);
 	}
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
@@ -67,5 +67,6 @@ void dce110_fill_display_configs(
 
 uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context);
 
+void dp_receiver_power_ctrl(struct dc_link *link, bool on);
 #endif /* __DC_HWSS_DCE110_H__ */