From: Wenjing Liu <Wenjing.Liu@amd.com>
Date: Wed, 23 Aug 2017 17:02:34 -0400
Subject: drm/amd/display: do not reset lane count in EQ fallback
Git-commit: 1cf49dea28dfc76f0816a4bc73c2ab975c72f55d
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
[Description]
According to DP1.4 specs we should not reset lane count back
when falling back in failing EQ training.
This causes PHY test pattern compliance to fail as infinite LT
when LT fails EQ to 4 RBR and fails CR in a loop.
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 --
1 file changed, 2 deletions(-)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1302,8 +1302,6 @@ bool decide_fallback_link_setting(
current_link_setting->lane_count);
} else if (!reached_minimum_link_rate
(current_link_setting->link_rate)) {
- current_link_setting->lane_count =
- initial_link_settings.lane_count;
current_link_setting->link_rate =
reduce_link_rate(
current_link_setting->link_rate);