From: Tony Cheng <tony.cheng@amd.com>
Date: Tue, 26 Sep 2017 01:56:00 -0400
Subject: drm/amd/display: option to maximize lb usage
Git-commit: 966869d07aae2d1becfcb16b55cafd4aae3c6627
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

experimental change for testing if max line buffer result in better stutter efficiency

for 1080p, LB can hold up to 9 line at 10bpcc, potentially add 10 line time of
latency hiding.

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h                   |    8 ++++++--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c |    3 +++
 2 files changed, 9 insertions(+), 2 deletions(-)

--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -181,15 +181,19 @@ struct dc_debug {
 	bool timing_trace;
 	bool clock_trace;
 	bool validation_trace;
+
+	/* stutter efficiency related */
 	bool disable_stutter;
+	bool use_max_lb;
 	enum dcc_option disable_dcc;
+	enum pipe_split_policy pipe_split_policy;
+	bool force_single_disp_pipe_split;
+
 	bool disable_dfs_bypass;
 	bool disable_dpp_power_gate;
 	bool disable_hubp_power_gate;
 	bool disable_pplib_wm_range;
 	bool use_dml_wm;
-	enum pipe_split_policy pipe_split_policy;
-	bool force_single_disp_pipe_split;
 	unsigned int min_disp_clk_khz;
 	int sr_exit_time_dpm0_ns;
 	int sr_enter_plus_exit_time_dpm0_ns;
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
@@ -507,6 +507,9 @@ static enum lb_memory_config find_lb_mem
 {
 	enum lb_memory_config mem_cfg = LB_MEMORY_CONFIG_0;
 
+	if (xfm->base.ctx->dc->debug.use_max_lb)
+		return mem_cfg;
+
 	if (xfm->tf_mask->PIXEL_DEPTH) {
 		mem_cfg = dpp10_find_lb_memory_config(scl_data);
 	}