From: David Panariti <David.Panariti@amd.com>
Date: Fri, 15 Sep 2017 13:25:38 -0400
Subject: drm/amdgpu: New header for fields needed to determine state of ECC.
Git-commit: 26f1108525c7f085fd5e555d4b62e7bba42a723b
Patch-mainline: v4.16-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
Add header files with ECC related definitions
(MASKs, SHIFTs, DEFAULTs and OFFSETS).
Signed-off-by: David Panariti <David.Panariti@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h | 31 +++++
drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h | 52 ++++++++++
drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h | 36 ++++++
3 files changed, 119 insertions(+)
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _umc_6_0_DEFAULT_HEADER
+#define _umc_6_0_DEFAULT_HEADER
+
+#define mmUMCCH0_0_EccCtrl_DEFAULT 0x00000000
+
+#define mmUMCCH0_0_UMC_CONFIG_DEFAULT 0x00000203
+
+#define mmUMCCH0_0_UmcLocalCap_DEFAULT 0x00000000
+
+#endif
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _umc_6_0_OFFSET_H_
+#define _umc_6_0_OFFSET_H_
+
+#define mmUMCCH0_0_EccCtrl 0x0053
+#define mmUMCCH0_0_EccCtrl_BASE_IDX 0
+#define mmUMCCH1_0_EccCtrl 0x0853
+#define mmUMCCH1_0_EccCtrl_BASE_IDX 0
+#define mmUMCCH2_0_EccCtrl 0x1053
+#define mmUMCCH2_0_EccCtrl_BASE_IDX 0
+#define mmUMCCH3_0_EccCtrl 0x1853
+#define mmUMCCH3_0_EccCtrl_BASE_IDX 0
+
+#define mmUMCCH0_0_UMC_CONFIG 0x0040
+#define mmUMCCH0_0_UMC_CONFIG_BASE_IDX 0
+#define mmUMCCH1_0_UMC_CONFIG 0x0840
+#define mmUMCCH1_0_UMC_CONFIG_BASE_IDX 0
+#define mmUMCCH2_0_UMC_CONFIG 0x1040
+#define mmUMCCH2_0_UMC_CONFIG_BASE_IDX 0
+#define mmUMCCH3_0_UMC_CONFIG 0x1840
+#define mmUMCCH3_0_UMC_CONFIG_BASE_IDX 0
+
+#define mmUMCCH0_0_UmcLocalCap 0x0306
+#define mmUMCCH0_0_UmcLocalCap_BASE_IDX 0
+#define mmUMCCH1_0_UmcLocalCap 0x0b06
+#define mmUMCCH1_0_UmcLocalCap_BASE_IDX 0
+#define mmUMCCH2_0_UmcLocalCap 0x1306
+#define mmUMCCH2_0_UmcLocalCap_BASE_IDX 0
+#define mmUMCCH3_0_UmcLocalCap 0x1b06
+#define mmUMCCH3_0_UmcLocalCap_BASE_IDX 0
+
+#endif
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _umc_6_0_SH_MASK_HEADER
+#define _umc_6_0_SH_MASK_HEADER
+
+#define UMCCH0_0_EccCtrl__RdEccEn_MASK 0x00000400L
+#define UMCCH0_0_EccCtrl__RdEccEn__SHIFT 0xa
+#define UMCCH0_0_EccCtrl__WrEccEn_MASK 0x00000001L
+#define UMCCH0_0_EccCtrl__WrEccEn__SHIFT 0x0
+
+#define UMCCH0_0_UMC_CONFIG__DramReady_MASK 0x80000000L
+#define UMCCH0_0_UMC_CONFIG__DramReady__SHIFT 0x1f
+
+#define UMCCH0_0_UmcLocalCap__EccDis_MASK 0x00000001L
+#define UMCCH0_0_UmcLocalCap__EccDis__SHIFT 0x0
+
+#endif