From: Andrew Jiang <Andrew.Jiang@amd.com>
Date: Tue, 14 Nov 2017 12:40:20 -0500
Subject: drm/amd/display: Set OPP default values in init_hw
Git-commit: 621fd3e39fc0222d7c8d95ddb5a2dff6261a0a86
Patch-mainline: v4.16-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

On S3 resume, we do not reconstruct OPP, but we do need to
reinitialize some of its values to the default ones.
Therefore, move those lines out of the OPP constructor and
into init_hw.

Also reset the hubp power gated flag, since nothing is
power gated at init_hw.

Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c |   16 ++++++++++----
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c          |    7 ------
 2 files changed, 12 insertions(+), 11 deletions(-)

--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -743,13 +743,21 @@ static void dcn10_init_hw(struct dc *dc)
 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+		struct output_pixel_processor *opp = dc->res_pool->opps[i];
+		struct mpc_tree_cfg *mpc_tree = &opp->mpc_tree;
+		struct hubp *hubp = dc->res_pool->hubps[i];
+
+		mpc_tree->dpp[0] = i;
+		mpc_tree->mpcc[0] = i;
+		mpc_tree->num_pipes = 1;
 
 		pipe_ctx->stream_res.tg = tg;
 		pipe_ctx->pipe_idx = i;
-		pipe_ctx->plane_res.hubp = dc->res_pool->hubps[i];
-		pipe_ctx->plane_res.hubp->mpcc_id = i;
-		pipe_ctx->plane_res.hubp->opp_id =
-				dc->res_pool->mpc->funcs->get_opp_id(dc->res_pool->mpc, i);
+
+		pipe_ctx->plane_res.hubp = hubp;
+		hubp->mpcc_id = i;
+		hubp->opp_id = dc->res_pool->mpc->funcs->get_opp_id(dc->res_pool->mpc, i);
+		hubp->power_gated = false;
 
 		plane_atomic_disconnect(dc, pipe_ctx);
 	}
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -330,17 +330,10 @@ void dcn10_opp_construct(struct dcn10_op
 	const struct dcn10_opp_shift *opp_shift,
 	const struct dcn10_opp_mask *opp_mask)
 {
-	int i;
 	oppn10->base.ctx = ctx;
 	oppn10->base.inst = inst;
 	oppn10->base.funcs = &dcn10_opp_funcs;
 
-	oppn10->base.mpc_tree.dpp[0] = inst;
-	oppn10->base.mpc_tree.mpcc[0] = inst;
-	oppn10->base.mpc_tree.num_pipes = 1;
-	for (i = 0; i < MAX_PIPES; i++)
-		oppn10->base.mpcc_disconnect_pending[i] = false;
-
 	oppn10->regs = regs;
 	oppn10->opp_shift = opp_shift;
 	oppn10->opp_mask = opp_mask;