From: Tony Cheng <tony.cheng@amd.com>
Date: Wed, 22 Nov 2017 11:51:30 -0500
Subject: drm/amd/display: really fix time out in init sequence
Git-commit: 75c2dec31a100daee4d3d9a1c2042918c9561f04
Patch-mainline: v4.16-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

REG_UPDATE_2 return the reg value it write out through MMIO
we need to do a REG_READ to confirm the value is written out

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -42,13 +42,14 @@ void hubp1_set_blank(struct hubp *hubp,
 {
 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 	uint32_t blank_en = blank ? 1 : 0;
-	uint32_t reg_val = 0;
 
-	reg_val = REG_UPDATE_2(DCHUBP_CNTL,
+	REG_UPDATE_2(DCHUBP_CNTL,
 			HUBP_BLANK_EN, blank_en,
 			HUBP_TTU_DISABLE, blank_en);
 
 	if (blank) {
+		uint32_t reg_val = REG_READ(DCHUBP_CNTL);
+
 		if (reg_val) {
 			/* init sequence workaround: in case HUBP is
 			 * power gated, this wait would timeout.