From: Lucas Stach <l.stach@pengutronix.de>
Date: Fri, 4 May 2018 11:58:45 +0200
Subject: drm/etnaviv: mmuv2: support 40 bit phys address
Git-commit: 931e97f3afd80bd9671d92f6934306a56012cae8
Patch-mainline: v4.18-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

MMUv2 supports up to 40 bits of physical address by folding the upper
8 bits into bits [4:11] of the PTE.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

--- a/drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c
@@ -87,11 +87,14 @@ static int etnaviv_iommuv2_map(struct et
 	struct etnaviv_iommuv2_domain *etnaviv_domain =
 			to_etnaviv_domain(domain);
 	int mtlb_entry, stlb_entry, ret;
-	u32 entry = (u32)paddr | MMUv2_PTE_PRESENT;
+	u32 entry = lower_32_bits(paddr) | MMUv2_PTE_PRESENT;
 
 	if (size != SZ_4K)
 		return -EINVAL;
 
+	if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
+		entry |= (upper_32_bits(paddr) & 0xff) << 4;
+
 	if (prot & ETNAVIV_PROT_WRITE)
 		entry |= MMUv2_PTE_WRITEABLE;