From 0870a2a4a3d0aab568ce5729bd99f43f96825f85 Mon Sep 17 00:00:00 2001
From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Date: Tue, 10 Oct 2017 22:30:08 +0100
Subject: [PATCH] drm/i915: Create generic function to setup LLC ring frequency table
Git-commit: 0870a2a4a3d0aab568ce5729bd99f43f96825f85
Patch-mainline: v4.15-rc1
References: FATE#322643 bsc#1055900

Prepared intel_update_ring_freq function to setup ring frequency
for applicable platforms determined by macro HAS_LLC.

V2: Replaced NEEDS_RING_FREQ_UPDATE with HAS_LLC macro. (Chris)    Added check while calling from intel_enable_gt_powersave.

V3: s/intel_update_ring_freq/intel_enable_llc_pstate and created
new placeholder function intel_disable_llc_pstate. (Chris)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-11-git-send-email-sagar.a.kamble@intel.com
Acked-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010213010.7415-10-chris@chris-wilson.co.uk
Acked-by: Takashi Iwai <tiwai@suse.de>

---
 drivers/gpu/drm/i915/intel_pm.c |   24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7973,6 +7973,13 @@ void intel_sanitize_gt_powersave(struct
 	gen6_reset_rps_interrupts(dev_priv);
 }
 
+static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
+{
+	lockdep_assert_held(&i915->pcu_lock);
+
+	/* Currently there is no HW configuration to be done to disable. */
+}
+
 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
@@ -7998,10 +8005,20 @@ void intel_disable_gt_powersave(struct d
 		ironlake_disable_drps(dev_priv);
 	}
 
+	if (HAS_LLC(dev_priv))
+		intel_disable_llc_pstate(dev_priv);
+
 	rps->enabled = false;
 	mutex_unlock(&dev_priv->pcu_lock);
 }
 
+static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
+{
+	lockdep_assert_held(&i915->pcu_lock);
+
+	gen6_update_ring_freq(i915);
+}
+
 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
@@ -8027,21 +8044,20 @@ void intel_enable_gt_powersave(struct dr
 	} else if (INTEL_GEN(dev_priv) >= 9) {
 		gen9_enable_rc6(dev_priv);
 		gen9_enable_rps(dev_priv);
-		if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
-			gen6_update_ring_freq(dev_priv);
 	} else if (IS_BROADWELL(dev_priv)) {
 		gen8_enable_rc6(dev_priv);
 		gen8_enable_rps(dev_priv);
-		gen6_update_ring_freq(dev_priv);
 	} else if (INTEL_GEN(dev_priv) >= 6) {
 		gen6_enable_rc6(dev_priv);
 		gen6_enable_rps(dev_priv);
-		gen6_update_ring_freq(dev_priv);
 	} else if (IS_IRONLAKE_M(dev_priv)) {
 		ironlake_enable_drps(dev_priv);
 		intel_init_emon(dev_priv);
 	}
 
+	if (HAS_LLC(dev_priv))
+		intel_enable_llc_pstate(dev_priv);
+
 	WARN_ON(rps->max_freq < rps->min_freq);
 	WARN_ON(rps->idle_freq > rps->max_freq);