From a86af2314a867804bb1531d514aa25c264fe5cb9 Mon Sep 17 00:00:00 2001
From: Michal Wajdeczko <michal.wajdeczko@intel.com>
Date: Fri, 3 Nov 2017 15:18:13 +0000
Subject: [PATCH] drm/i915/guc: Wait for ucode DMA transfer completion
Git-commit: a86af2314a867804bb1531d514aa25c264fe5cb9
Patch-mainline: v4.16-rc1
References: FATE#322643 bsc#1055900
We silently assumed that DMA transfer will be completed
within assumed timeout and thus we were waiting only at
last step for GuC to become ready. Add intermediate wait
to catch unexpected delays in DMA transfer.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171103151816.62048-2-michal.wajdeczko@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Takashi Iwai <tiwai@suse.de>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -160,6 +160,8 @@ static int guc_xfer_ucode(struct intel_g
struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct intel_uc_fw *guc_fw = &guc->fw;
unsigned long offset;
+ u32 status;
+ int ret;
/*
* The header plus uCode will be copied to WOPCM via DMA, excluding any
@@ -182,7 +184,12 @@ static int guc_xfer_ucode(struct intel_g
/* Finally start the DMA */
I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
- return 0;
+ /* Wait for DMA to finish */
+ ret = __intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0,
+ 2, 100, &status);
+ DRM_DEBUG_DRIVER("GuC DMA status %#x\n", status);
+
+ return ret;
}
/*